From: Nicolai Hähnle <nicolai.haeh...@amd.com>
This fixes arb_shader_image_load_store-host-mem-barrier.
---
src/gallium/drivers/radeonsi/si_state.c | 7 +++++--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_state.c
b/src/gallium/drivers/radeonsi/si_state.c
index 6dcd532..4093921 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -3535,7 +3535,9 @@ static void si_memory_barrier(struct pipe_context *ctx,
unsigned flags)
if (flags & (PIPE_BARRIER_VERTEX_BUFFER |
PIPE_BARRIER_SHADER_BUFFER |
PIPE_BARRIER_TEXTURE |
- PIPE_BARRIER_IMAGE)) {
+ PIPE_BARRIER_IMAGE |
+ PIPE_BARRIER_INDEX_BUFFER |
+ PIPE_BARRIER_STREAMOUT_BUFFER)) {
/* As far as I can tell, L1 contents are written back to L2
* automatically at end of shader, but the contents of other
* L1 caches might still be stale. */
@@ -3546,7 +3548,8 @@ static void si_memory_barrier(struct pipe_context *ctx,
unsigned flags)
sctx->b.flags |= SI_CONTEXT_FLUSH_AND_INV_FRAMEBUFFER;
if (flags & (PIPE_BARRIER_MAPPED_BUFFER |
- PIPE_BARRIER_FRAMEBUFFER)) {
+ PIPE_BARRIER_FRAMEBUFFER |
+ PIPE_BARRIER_INDIRECT_BUFFER)) {
/* Not sure if INV_GLOBAL_L2 is the best thing here.
*
* We need to make sure that TC L1 & L2 are written back to
--
2.5.0
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