We can then upload only the dirty ones with the constant engine.
Signed-off-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl>
---
src/gallium/drivers/radeonsi/si_descriptors.c | 23 +++++++++++++++++++++++
src/gallium/drivers/radeonsi/si_state.h | 1 +
2 files changed, 24 insertions(+)
diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c
b/src/gallium/drivers/radeonsi/si_descriptors.c
index b5557d8..d893ab4 100644
--- a/src/gallium/drivers/radeonsi/si_descriptors.c
+++ b/src/gallium/drivers/radeonsi/si_descriptors.c
@@ -108,6 +108,7 @@ static void si_init_descriptors(struct si_descriptors *desc,
desc->element_dw_size = element_dw_size;
desc->num_elements = num_elements;
desc->list_dirty = true; /* upload the list before the next draw */
+ desc->dirty_mask = num_elements == 64 ? ~0llu : (1llu << num_elements)
- 1;
desc->shader_userdata_offset = shader_userdata_index * 4;
/* Initialize the array to NULL descriptors if the element size is 8. */
@@ -188,6 +189,9 @@ static void si_sampler_views_begin_new_cs(struct si_context
*sctx,
si_sampler_view_add_buffer(sctx, views->views[i]->texture);
}
+ views->desc.dirty_mask = views->desc.num_elements == 64 ? ~0llu :
+ (1llu << views->desc.num_elements) - 1;
+
if (!views->desc.buffer)
return;
radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, views->desc.buffer,
@@ -239,6 +243,7 @@ static void si_set_sampler_view(struct si_context *sctx,
views->desc.enabled_mask &= ~(1llu << slot);
}
+ views->desc.dirty_mask |= 1llu << slot;
views->desc.list_dirty = true;
}
@@ -345,6 +350,9 @@ si_image_views_begin_new_cs(struct si_context *sctx, struct
si_images_info *imag
si_sampler_view_add_buffer(sctx, view->resource);
}
+ images->desc.dirty_mask = images->desc.num_elements == 64 ? ~0llu :
+ (1llu << images->desc.num_elements) - 1;
+
if (images->desc.buffer) {
radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
images->desc.buffer,
@@ -362,6 +370,7 @@ si_disable_shader_image(struct si_images_info *images,
unsigned slot)
memcpy(images->desc.list + slot*8, null_image_descriptor, 8*4);
images->desc.enabled_mask &= ~(1llu << slot);
+ images->desc.dirty_mask |= 1llu << slot;
images->desc.list_dirty = true;
}
}
@@ -443,6 +452,7 @@ si_set_shader_images(struct pipe_context *pipe, unsigned
shader,
}
images->desc.enabled_mask |= 1llu << slot;
+ images->desc.dirty_mask |= 1llu << slot;
images->desc.list_dirty = true;
}
}
@@ -501,6 +511,7 @@ static void si_bind_sampler_states(struct pipe_context
*ctx, unsigned shader,
continue;
memcpy(desc->list + slot * 16 + 12, sstates[i]->val, 4*4);
+ desc->dirty_mask |= 1llu << slot;
desc->list_dirty = true;
}
}
@@ -547,6 +558,9 @@ static void si_buffer_resources_begin_new_cs(struct
si_context *sctx,
buffers->shader_usage, buffers->priority);
}
+ buffers->desc.dirty_mask = buffers->desc.num_elements == 64 ? ~0llu :
+ (1llu << buffers->desc.num_elements) - 1;
+
if (!buffers->desc.buffer)
return;
radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
@@ -743,6 +757,7 @@ static void si_set_constant_buffer(struct pipe_context
*ctx, uint shader, uint s
buffers->desc.enabled_mask &= ~(1llu << slot);
}
+ buffers->desc.dirty_mask |= 1llu << slot;
buffers->desc.list_dirty = true;
}
@@ -790,6 +805,7 @@ static void si_set_shader_buffers(struct pipe_context *ctx,
unsigned shader,
radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, buf,
buffers->shader_usage, buffers->priority);
buffers->desc.enabled_mask |= 1llu << slot;
+ buffers->desc.dirty_mask |= 1llu << slot;
}
buffers->desc.list_dirty = true;
@@ -887,6 +903,7 @@ void si_set_ring_buffer(struct pipe_context *ctx, uint
shader, uint slot,
buffers->desc.enabled_mask &= ~(1llu << slot);
}
+ buffers->desc.dirty_mask |= 1llu << slot;
buffers->desc.list_dirty = true;
}
@@ -985,6 +1002,7 @@ static void si_set_streamout_targets(struct pipe_context
*ctx,
NULL);
buffers->desc.enabled_mask &= ~(1llu << bufidx);
}
+ buffers->desc.dirty_mask |= 1llu << bufidx;
}
for (; i < old_num_targets; i++) {
bufidx = SI_SO_BUF_OFFSET + i;
@@ -992,6 +1010,7 @@ static void si_set_streamout_targets(struct pipe_context
*ctx,
memset(buffers->desc.list + bufidx*4, 0, sizeof(uint32_t) * 4);
pipe_resource_reference(&buffers->buffers[bufidx], NULL);
buffers->desc.enabled_mask &= ~(1llu << bufidx);
+ buffers->desc.dirty_mask |= 1llu << bufidx;
}
buffers->desc.list_dirty = true;
@@ -1046,6 +1065,7 @@ static void si_reset_buffer_resources(struct si_context
*sctx,
si_desc_reset_buffer_offset(&sctx->b.b,
buffers->desc.list + i*4,
old_va, buf);
+ buffers->desc.dirty_mask |= 1llu << i;
buffers->desc.list_dirty = true;
radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
@@ -1108,6 +1128,7 @@ static void si_invalidate_buffer(struct pipe_context
*ctx, struct pipe_resource
if (buffers->buffers[i] == buf) {
si_desc_reset_buffer_offset(ctx,
buffers->desc.list + i*4,
old_va, buf);
+ buffers->desc.dirty_mask |= 1llu << i;
buffers->desc.list_dirty = true;
radeon_add_to_buffer_list(&sctx->b,
&sctx->b.gfx,
@@ -1153,6 +1174,7 @@ static void si_invalidate_buffer(struct pipe_context
*ctx, struct pipe_resource
views->desc.list +
i * 16 + 4,
old_va, buf);
+ views->desc.dirty_mask |= 1llu << i;
views->desc.list_dirty = true;
radeon_add_to_buffer_list(&sctx->b,
&sctx->b.gfx,
@@ -1174,6 +1196,7 @@ static void si_invalidate_buffer(struct pipe_context
*ctx, struct pipe_resource
si_desc_reset_buffer_offset(
ctx, images->desc.list + i * 8 + 4,
old_va, buf);
+ images->desc.dirty_mask |= 1llu << i;
images->desc.list_dirty = true;
radeon_add_to_buffer_list(
diff --git a/src/gallium/drivers/radeonsi/si_state.h
b/src/gallium/drivers/radeonsi/si_state.h
index 6748f80..a0dc896 100644
--- a/src/gallium/drivers/radeonsi/si_state.h
+++ b/src/gallium/drivers/radeonsi/si_state.h
@@ -200,6 +200,7 @@ struct si_descriptors {
/* The i-th bit is set if that element is enabled (non-NULL resource).
*/
uint64_t enabled_mask;
+ uint64_t dirty_mask; /* needed by the CE for partial updates */
/* The shader userdata offset within a shader where the 64-bit pointer
to the descriptor
* array will be stored. */
--
2.8.0
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