This series adds blorp pipeline upload support for gen8 and gen9, switches over to blorp blits (except for 2X and 16X msaa which don't have support in blorp yet) and finally re-introduces blorp clears for gen6-9. This makes it possible to close bug 94181 preventing single sample compression getting enabled.
First two patches are not mandatory, they are just something I wrote during debugging. There are quite a few patches that simply make either core i965 pipeline upload logic or meta fast clear utilities available for blorp to re-use. Most important is the texture surface setup for gen8/9 - blorp specific logic is only introduced for render target setup. I already have follow-up plans for this also where the aim is to drop all blorp specific surface setup logic by re-using core i965 upload instead. Among other things this provides easy switch to layered clears using instance identifier. Re-introduction of blorp clears is slightly modified as the original didn't integrate with the current driver. I also chose to drop some logic and re-use gen9 aware counterparts from i965-meta. Patches 34-39 are optimizations reducing state trashing. These are needed to avoid performance regressions in a few synthetic benchmarks. A few synthetic cases were improved even without. This series doesn't remove any meta logic yet. Simple reverts of i965/blorp: Enable blits on gen8 i965/blorp: Enable for normal color clears i965/blorp: Enable for buffer resolves allow us to move back to meta if needs be. Big thanks to Ken for helping in debugging!! Topi Pohjolainen (40): i965/gen9: Use correct size for DS_STATE i965/gen8: Document inst buffer size modify enabling bit i965/gen8: Expose surface state helpers i965/gen8: Expose state base address setup i965/blorp: Let compiler calculate the vertex buffer size i965/blorp/gen7: Prepare re-using for gen8 i965/blorp: Use 8k chunk size for urb allocation i965/blorp/gen7: Expose state setup applicable to gen8 i965/blorp/gen6: Prepare vertex buffer setup logic for gen8 i965/blorp: Prepare render target write for gen8 i965/blorp: Prepare sampling for gen9 i965: Allow texture surface state setup to be used by blorp i965/blorp: Pipeline upload support for gen8 i965/blorp: Add support for source swizzle i965/blorp: Add support for sampling 3D textures i965/blorp: Add check for supported sample numbers i965/blorp: Prepare stencil sampling for gen8 i965/blorp: Enable blits on gen8 i965/blorp: Add support for setting fast clear operation i965/blorp: Add support for disabling color blending i965/blorp: Reduce scope for generator and its inputs i965/blorp: Switch the order of render and texture targets i965: Declare input to mcs alignment calculation constant i965/meta: Expose fast clear rectangle calculation i965/meta: Expose resolve clear rectangle calculation i965/meta: Expose non-fast clear rectangle calculation i965/meta: Expose fast clear value setup i965/meta: Expose check for fast clear compatibility i965/meta: Move check for srgb into is_color_fast_clear_compatible() i965/blorp: Re-introduce clear programs i965/blorp: Skip uploading state/options not needed for clears i965/blorp/gen7: Prepare blorp being the very first renderer i965/blorp: Prepare to switch from compute pipeline i965/blorp: Skip re-emitting urb config whenever possible i965/blorp: Do not tricker urb re-configuration unnecessarily i965/blorp: Reconfigure base state address only if needed i965/blorp: Leave new batch signaling to batch buffer logic i965/blorp: Use more fine grained state trashing than new context i965/blorp: Enable for normal color clears i965/blorp: Enable for buffer resolves src/mesa/drivers/dri/i965/Makefile.sources | 2 + src/mesa/drivers/dri/i965/brw_blorp.cpp | 30 +- src/mesa/drivers/dri/i965/brw_blorp.h | 72 ++- src/mesa/drivers/dri/i965/brw_blorp_blit.cpp | 92 ++- src/mesa/drivers/dri/i965/brw_blorp_blit_eu.cpp | 29 +- src/mesa/drivers/dri/i965/brw_blorp_blit_eu.h | 8 +- src/mesa/drivers/dri/i965/brw_blorp_clear.cpp | 460 ++++++++++++++ src/mesa/drivers/dri/i965/brw_clear.c | 9 + src/mesa/drivers/dri/i965/brw_context.h | 5 +- src/mesa/drivers/dri/i965/brw_fs.h | 2 +- src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 11 +- src/mesa/drivers/dri/i965/brw_meta_fast_clear.c | 160 ++--- src/mesa/drivers/dri/i965/brw_meta_util.h | 29 + src/mesa/drivers/dri/i965/brw_state.h | 18 + src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 3 +- src/mesa/drivers/dri/i965/gen6_blorp.cpp | 84 ++- src/mesa/drivers/dri/i965/gen7_blorp.cpp | 89 ++- src/mesa/drivers/dri/i965/gen7_wm_surface_state.c | 7 +- src/mesa/drivers/dri/i965/gen8_blorp.cpp | 715 ++++++++++++++++++++++ src/mesa/drivers/dri/i965/gen8_ds_state.c | 22 +- src/mesa/drivers/dri/i965/gen8_misc_state.c | 6 +- src/mesa/drivers/dri/i965/gen8_surface_state.c | 58 +- src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 17 +- src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 2 +- 24 files changed, 1695 insertions(+), 235 deletions(-) create mode 100644 src/mesa/drivers/dri/i965/brw_blorp_clear.cpp create mode 100644 src/mesa/drivers/dri/i965/gen8_blorp.cpp -- 2.5.5 _______________________________________________ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev