This makes header_regs available for computing VUE offsets within clip code. --- src/mesa/drivers/dri/i965/brw_clip.c | 9 ++++----- src/mesa/drivers/dri/i965/brw_clip.h | 1 + 2 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_clip.c b/src/mesa/drivers/dri/i965/brw_clip.c index f5ae966..f33518b 100644 --- a/src/mesa/drivers/dri/i965/brw_clip.c +++ b/src/mesa/drivers/dri/i965/brw_clip.c @@ -58,7 +58,6 @@ static void compile_clip_prog( struct brw_context *brw, GLuint program_size; GLuint delta; GLuint i; - GLuint header_regs; memset(&c, 0, sizeof(c)); @@ -78,11 +77,11 @@ static void compile_clip_prog( struct brw_context *brw, * These are currently hardcoded: */ if (intel->gen == 5) - header_regs = 3; + c.header_regs = 3; else - header_regs = 1; + c.header_regs = 1; - delta = header_regs * REG_SIZE; + delta = c.header_regs * REG_SIZE; for (i = 0; i < VERT_RESULT_MAX; i++) { if (c.key.attrs & BITFIELD64_BIT(i)) { @@ -99,7 +98,7 @@ static void compile_clip_prog( struct brw_context *brw, * length. nr_regs determines the urb_read_length from the start * of the header to the end of the vertex data. */ - c.nr_regs = header_regs + (c.nr_attrs + 1) / 2; + c.nr_regs = c.header_regs + (c.nr_attrs + 1) / 2; c.nr_bytes = c.nr_regs * REG_SIZE; diff --git a/src/mesa/drivers/dri/i965/brw_clip.h b/src/mesa/drivers/dri/i965/brw_clip.h index abd35d2..0324fea 100644 --- a/src/mesa/drivers/dri/i965/brw_clip.h +++ b/src/mesa/drivers/dri/i965/brw_clip.h @@ -115,6 +115,7 @@ struct brw_clip_compile { GLboolean need_direction; + GLuint header_regs; /** Mapping from VERT_RESULT_* to offset within the VUE. */ GLuint offset[VERT_RESULT_MAX]; /** Mapping from attribute index to VERT_RESULT_* */ -- 1.7.6 _______________________________________________ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev