Samuel Iglesias Gonsálvez <sigles...@igalia.com> writes:
> From: Connor Abbott <connor.w.abb...@intel.com>
>
> Similar to retype() and offset().
> ---
> src/mesa/drivers/dri/i965/brw_ir_fs.h | 8 ++++++++
> 1 file changed, 8 insertions(+)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_ir_fs.h
> b/src/mesa/drivers/dri/i965/brw_ir_fs.h
> index e4f20f4..abda2c3 100644
> --- a/src/mesa/drivers/dri/i965/brw_ir_fs.h
> +++ b/src/mesa/drivers/dri/i965/brw_ir_fs.h
> @@ -78,6 +78,14 @@ retype(fs_reg reg, enum brw_reg_type type)
> }
>
> static inline fs_reg
> +stride(fs_reg reg, unsigned stride)
> +{
> + if (reg.stride != 0)
> + reg.stride = stride;
> + return reg;
> +}
> +
This only works if reg.stride == 0 or 1, we need to honour the stride of
the original register (e.g. by doing reg.stride *= stride) or you'll end
up taking components not part of the region given as argument. It gets
messy with ARF and HW registers because they represent the stride
differently... I suggest that instead of fixing this you take the
following patch from my SIMD32 branch that introduces a somewhat easier
to use helper: Instead of doing 'stride(horiz_offset(retype(reg, t), i),
type_sz(reg.type) / type_sz(t))' to take the i-th subcomponent of type t
of the original register you would just do 'subscript(reg, t, i)'. I
think I've looked through all the uses of stride() in your branch and
they are all sort of an open-coded version of subscript(). This will
also address the issue Ken pointed out in patch 29 related to the use of
horiz_offset() on uniforms (or anything with stride other than one,
really) -- See the attached patch (yes, correct ARF/HW reg handling will
be required for SIMD32...).
> +static inline fs_reg
> byte_offset(fs_reg reg, unsigned delta)
> {
> switch (reg.file) {
> --
> 2.5.0
>
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From d949c68042ca59429067b87d2e1e1f95c558d10c Mon Sep 17 00:00:00 2001
From: Francisco Jerez <curroje...@riseup.net>
Date: Mon, 2 May 2016 16:10:28 -0700
Subject: [PATCH] i965/fs: Introduce helper to extract a field from each
channel of a register.
---
src/mesa/drivers/dri/i965/brw_ir_fs.h | 28 ++++++++++++++++++++++++++++
1 file changed, 28 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_ir_fs.h b/src/mesa/drivers/dri/i965/brw_ir_fs.h
index e4f20f4..1649da3 100644
--- a/src/mesa/drivers/dri/i965/brw_ir_fs.h
+++ b/src/mesa/drivers/dri/i965/brw_ir_fs.h
@@ -165,6 +165,34 @@ half(fs_reg reg, unsigned idx)
return reg;
}
+/**
+ * Reinterpret each channel of register \p reg as a vector of values of the
+ * given smaller type and take the i-th subcomponent from each.
+ */
+static inline fs_reg
+subscript(fs_reg reg, brw_reg_type type, unsigned i)
+{
+ assert((i + 1) * type_sz(type) <= type_sz(reg.type));
+
+ if (reg.file == ARF || reg.file == FIXED_GRF) {
+ /* The stride is encoded inconsistently for fixed GRF and ARF registers
+ * as the log2 of the actual vertical and horizontal strides.
+ */
+ const int delta = _mesa_logbase2(type_sz(reg.type)) -
+ _mesa_logbase2(type_sz(type));
+ reg.hstride += (reg.hstride ? delta : 0);
+ reg.vstride += (reg.vstride ? delta : 0);
+
+ } else if (reg.file == IMM) {
+ assert(reg.type == type);
+
+ } else {
+ reg.stride *= type_sz(reg.type) / type_sz(type);
+ }
+
+ return byte_offset(retype(reg, type), i * type_sz(type));
+}
+
static const fs_reg reg_undef;
class fs_inst : public backend_instruction {
--
2.7.3
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