So they can be shared with other asics.
Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 22 ++++++++++++----------
1 file changed, 12 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index 7fcde08..36ec41f 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -5162,15 +5162,17 @@ static int gfx_v8_0_late_init(void *handle)
return 0;
}
-static void polaris11_enable_gfx_static_mg_power_gating(struct amdgpu_device
*adev,
- bool enable)
+static void gfx_v8_0_enable_gfx_static_mg_power_gating(struct amdgpu_device
*adev,
+ bool enable)
{
uint32_t data, temp;
- /* Send msg to SMU via Powerplay */
- amdgpu_set_powergating_state(adev,
- AMD_IP_BLOCK_TYPE_SMC,
- enable ? AMD_PG_STATE_GATE : AMD_PG_STATE_UNGATE);
+ if (adev->asic_type == CHIP_POLARIS11)
+ /* Send msg to SMU via Powerplay */
+ amdgpu_set_powergating_state(adev,
+ AMD_IP_BLOCK_TYPE_SMC,
+ enable ?
+ AMD_PG_STATE_GATE :
AMD_PG_STATE_UNGATE);
if (enable) {
/* Enable static MGPG */
@@ -5188,8 +5190,8 @@ static void
polaris11_enable_gfx_static_mg_power_gating(struct amdgpu_device *ad
}
}
-static void polaris11_enable_gfx_dynamic_mg_power_gating(struct amdgpu_device
*adev,
- bool enable)
+static void gfx_v8_0_enable_gfx_dynamic_mg_power_gating(struct amdgpu_device
*adev,
+ bool enable)
{
uint32_t data, temp;
@@ -5241,10 +5243,10 @@ static int gfx_v8_0_set_powergating_state(void *handle,
switch (adev->asic_type) {
case CHIP_POLARIS11:
if (adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG)
- polaris11_enable_gfx_static_mg_power_gating(adev,
+ gfx_v8_0_enable_gfx_static_mg_power_gating(adev,
state == AMD_PG_STATE_GATE ? true :
false);
else if (adev->pg_flags & AMD_PG_SUPPORT_GFX_DMG)
- polaris11_enable_gfx_dynamic_mg_power_gating(adev,
+ gfx_v8_0_enable_gfx_dynamic_mg_power_gating(adev,
state == AMD_PG_STATE_GATE ? true :
false);
else
polaris11_enable_gfx_quick_mg_power_gating(adev,
--
2.5.5
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