The tessellation evaluation stage generates source regions with a vstride=0
for these so they hit the gen7 hardware decompression bug. Split them to
prevent this.
---
src/mesa/drivers/dri/i965/brw_vec4.cpp | 13 ++++++++++++-
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/brw_vec4.cpp
b/src/mesa/drivers/dri/i965/brw_vec4.cpp
index 9b5d048..7ea94cd 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4.cpp
@@ -2029,6 +2029,7 @@ vec4_visitor::convert_to_hw_regs()
*/
static unsigned
get_lowered_simd_width(const struct brw_device_info *devinfo,
+ unsigned stage,
const vec4_instruction *inst)
{
/* For now we only need to split some cases of double-precision instructions
@@ -2064,8 +2065,17 @@ get_lowered_simd_width(const struct brw_device_info
*devinfo,
for (unsigned i = 0; i < 3; i++) {
if (inst->src[i].file == BAD_FILE)
continue;
+
if (inst->regs_read(i) < 2)
lowered_width = MIN2(lowered_width, 4);
+
+ /* The tessellation evaluation stage generates code with source regions
+ * that use a vstride 0 for all attributes, which makes them hit
+ * the associated instruction decompression bug in gen7. Split them
+ * to prevent this.
+ */
+ if (stage == MESA_SHADER_TESS_EVAL && inst->src[i].file == ATTR)
+ lowered_width = MIN2(lowered_width, 4);
}
return lowered_width;
@@ -2077,7 +2087,8 @@ vec4_visitor::lower_simd_width()
bool progress = false;
foreach_block_and_inst_safe(block, vec4_instruction, inst, cfg) {
- const unsigned lowered_width = get_lowered_simd_width(devinfo, inst);
+ const unsigned lowered_width =
+ get_lowered_simd_width(devinfo, stage, inst);
assert(lowered_width <= inst->exec_size);
if (lowered_width == inst->exec_size)
continue;
--
2.7.4
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