---
src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 21 ++++++++++++++++++---
1 file changed, 18 insertions(+), 3 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
index dd06a32..cf35f2e 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
@@ -1347,10 +1347,25 @@ vec4_visitor::nir_emit_alu(nir_alu_instr *instr)
case nir_op_flt:
case nir_op_fge:
case nir_op_feq:
- case nir_op_fne:
- emit(CMP(dst, op[0], op[1],
- brw_conditional_for_nir_comparison(instr->op)));
+ case nir_op_fne: {
+ enum brw_conditional_mod conditional_mod =
+ brw_conditional_for_nir_comparison(instr->op);
+ if (nir_src_bit_size(instr->src[0].src) < 64) {
+ emit(CMP(dst, op[0], op[1], conditional_mod));
+ } else {
+ /* Produce a 32-bit boolean result from the DF comparison by selecting
+ * only the low 32-bit in each DF produced. Do this in a temporary
+ * so we can then move from there to the result using align16 again
+ * to honor the original writemask.
+ */
+ dst_reg temp = dst_reg(this, glsl_type::dvec4_type);
+ emit(CMP(temp, op[0], op[1], conditional_mod));
+ dst_reg result = dst_reg(this, glsl_type::bvec4_type);
+ emit(VEC4_OPCODE_PICK_LOW_32BIT, result, src_reg(temp));
+ emit(MOV(dst, src_reg(result)));
+ }
break;
+ }
case nir_op_ball_iequal2:
case nir_op_ball_iequal3:
--
2.7.4
_______________________________________________
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev
