Iago Toral Quiroga <ito...@igalia.com> writes:
> ---
> src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 18 ++++++++++++++++++
> 1 file changed, 18 insertions(+)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
> b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
> index 1525a3d..4014020 100644
> --- a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
> @@ -1497,6 +1497,24 @@ vec4_visitor::nir_emit_alu(nir_alu_instr *instr)
> emit(CMP(dst, op[0], brw_imm_f(0.0f), BRW_CONDITIONAL_NZ));
> break;
>
> + case nir_op_d2b: {
> + /* two-argument instructions can't take 64-bit immediates */
> + dst_reg zero = dst_reg(this, glsl_type::dvec4_type);
> + emit(MOV(zero, brw_imm_df(0.0)));
> +
> + dst_reg tmp = dst_reg(this, glsl_type::dvec4_type);
> + emit(CMP(tmp, op[0], src_reg(zero), BRW_CONDITIONAL_NZ));
> +
> + /* Convert the double CMP result to a single boolean result. For that
> + * we take the low 32-bit chunk of each DF component in the result.
> + * and do a final MOV to honor the original writemask
> + */
> + dst_reg result = dst_reg(this, glsl_type::bvec4_type);
> + emit(VEC4_OPCODE_PICK_LOW_32BIT, result, src_reg(tmp));
> + emit(MOV(dst, src_reg(result)));Couldn't you just do a single CMP instruction of the double-precision argument and a single-precision 0.0 immediate? I think you could potentially also use a 32bit destination type on the CMP instruction so you don't need to emit the PICK_LOW+MOV instructions afterwards. It may hit an instruction decompression bug but it could be cleaned up by the SIMD lowering pass afterwards, AFAICT the result would be two uncompressed instructions instead of the two uncompressed plus two compressed instructions above. > + break; > + } > + > case nir_op_i2b: > emit(CMP(dst, op[0], brw_imm_d(0), BRW_CONDITIONAL_NZ)); > break; > -- > 2.7.4 > > _______________________________________________ > mesa-dev mailing list > mesa-dev@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/mesa-dev
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