From: Marek Olšák <marek.ol...@amd.com> --- src/gallium/winsys/amdgpu/drm/amdgpu_cs.c | 26 ++++++++++++-------------- 1 file changed, 12 insertions(+), 14 deletions(-)
diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c index 73c8a97..0bb916e 100644 --- a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c +++ b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c @@ -702,22 +702,20 @@ amdgpu_cs_add_const_preamble_ib(struct radeon_winsys_cs *rcs) cs->csc->request.number_of_ibs = 3; cs->csc->request.ibs = &cs->csc->ib[IB_CONST_PREAMBLE]; cs->cst->request.number_of_ibs = 3; cs->cst->request.ibs = &cs->cst->ib[IB_CONST_PREAMBLE]; return &cs->const_preamble_ib.base; } -#define OUT_CS(cs, value) (cs)->current.buf[(cs)->current.cdw++] = (value) - static int amdgpu_cs_lookup_buffer(struct radeon_winsys_cs *rcs, struct pb_buffer *buf) { struct amdgpu_cs *cs = amdgpu_cs(rcs); return amdgpu_lookup_buffer(cs->csc, (struct amdgpu_winsys_bo*)buf); } static bool amdgpu_cs_validate(struct radeon_winsys_cs *rcs) { @@ -765,28 +763,28 @@ static bool amdgpu_cs_check_space(struct radeon_winsys_cs *rcs, unsigned dw) assert(ib->used_ib_space == 0); va = amdgpu_winsys_bo(ib->big_ib_buffer)->va; /* This space was originally reserved. */ rcs->current.max_dw += 4; assert(ib->used_ib_space + 4 * rcs->current.max_dw <= ib->big_ib_buffer->size); /* Pad with NOPs and add INDIRECT_BUFFER packet */ while ((rcs->current.cdw & 7) != 4) - OUT_CS(rcs, 0xffff1000); /* type3 nop packet */ + radeon_emit(rcs, 0xffff1000); /* type3 nop packet */ - OUT_CS(rcs, PKT3(ib->ib_type == IB_MAIN ? PKT3_INDIRECT_BUFFER_CIK + radeon_emit(rcs, PKT3(ib->ib_type == IB_MAIN ? PKT3_INDIRECT_BUFFER_CIK : PKT3_INDIRECT_BUFFER_CONST, 2, 0)); - OUT_CS(rcs, va); - OUT_CS(rcs, va >> 32); + radeon_emit(rcs, va); + radeon_emit(rcs, va >> 32); new_ptr_ib_size = &rcs->current.buf[rcs->current.cdw]; - OUT_CS(rcs, S_3F2_CHAIN(1) | S_3F2_VALID(1)); + radeon_emit(rcs, S_3F2_CHAIN(1) | S_3F2_VALID(1)); assert((rcs->current.cdw & 7) == 0); assert(rcs->current.cdw <= rcs->current.max_dw); *ib->ptr_ib_size |= rcs->current.cdw; ib->ptr_ib_size = new_ptr_ib_size; /* Hook up the new chunk */ rcs->prev[rcs->num_prev].buf = rcs->current.buf; rcs->prev[rcs->num_prev].cdw = rcs->current.cdw; @@ -976,48 +974,48 @@ static int amdgpu_cs_flush(struct radeon_winsys_cs *rcs, struct amdgpu_winsys *ws = cs->ctx->ws; int error_code = 0; rcs->current.max_dw += amdgpu_cs_epilog_dws(cs->ring_type); switch (cs->ring_type) { case RING_DMA: /* pad DMA ring to 8 DWs */ if (ws->info.chip_class <= SI) { while (rcs->current.cdw & 7) - OUT_CS(rcs, 0xf0000000); /* NOP packet */ + radeon_emit(rcs, 0xf0000000); /* NOP packet */ } else { while (rcs->current.cdw & 7) - OUT_CS(rcs, 0x00000000); /* NOP packet */ + radeon_emit(rcs, 0x00000000); /* NOP packet */ } break; case RING_GFX: /* pad GFX ring to 8 DWs to meet CP fetch alignment requirements */ if (ws->info.gfx_ib_pad_with_type2) { while (rcs->current.cdw & 7) - OUT_CS(rcs, 0x80000000); /* type2 nop packet */ + radeon_emit(rcs, 0x80000000); /* type2 nop packet */ } else { while (rcs->current.cdw & 7) - OUT_CS(rcs, 0xffff1000); /* type3 nop packet */ + radeon_emit(rcs, 0xffff1000); /* type3 nop packet */ } /* Also pad the const IB. */ if (cs->const_ib.ib_mapped) while (!cs->const_ib.base.current.cdw || (cs->const_ib.base.current.cdw & 7)) - OUT_CS(&cs->const_ib.base, 0xffff1000); /* type3 nop packet */ + radeon_emit(&cs->const_ib.base, 0xffff1000); /* type3 nop packet */ if (cs->const_preamble_ib.ib_mapped) while (!cs->const_preamble_ib.base.current.cdw || (cs->const_preamble_ib.base.current.cdw & 7)) - OUT_CS(&cs->const_preamble_ib.base, 0xffff1000); + radeon_emit(&cs->const_preamble_ib.base, 0xffff1000); break; case RING_UVD: while (rcs->current.cdw & 15) - OUT_CS(rcs, 0x80000000); /* type2 nop packet */ + radeon_emit(rcs, 0x80000000); /* type2 nop packet */ break; default: break; } if (rcs->current.cdw > rcs->current.max_dw) { fprintf(stderr, "amdgpu: command stream overflowed\n"); } /* If the CS is not empty or overflowed.... */ -- 2.7.4 _______________________________________________ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev