Just say no to:
- brw->gs.base.prog_data = &brw->gs.prog_data->base.base;
We'll just use the brw_stage_prog_data pointer in brw_stage_state
and downcast it to brw_gs_prog_data as needed.
Signed-off-by: Kenneth Graunke <kenn...@whitecape.org>
---
src/mesa/drivers/dri/i965/brw_context.h | 1 -
src/mesa/drivers/dri/i965/brw_gs.c | 11 +++----
src/mesa/drivers/dri/i965/brw_gs_surface_state.c | 12 +++----
src/mesa/drivers/dri/i965/brw_state_cache.c | 1 -
src/mesa/drivers/dri/i965/gen6_clip_state.c | 10 +++---
src/mesa/drivers/dri/i965/gen6_gs_state.c | 18 ++++++-----
src/mesa/drivers/dri/i965/gen6_urb.c | 4 ++-
src/mesa/drivers/dri/i965/gen7_gs_state.c | 31 +++++++++---------
src/mesa/drivers/dri/i965/gen7_urb.c | 4 ++-
src/mesa/drivers/dri/i965/gen8_gs_state.c | 40 +++++++++++++-----------
10 files changed, 73 insertions(+), 59 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_context.h
b/src/mesa/drivers/dri/i965/brw_context.h
index 8c8f332..038c555 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -1118,7 +1118,6 @@ struct brw_context
struct {
struct brw_stage_state base;
- struct brw_gs_prog_data *prog_data;
/**
* True if the 3DSTATE_GS command most recently emitted to the 3D
diff --git a/src/mesa/drivers/dri/i965/brw_gs.c
b/src/mesa/drivers/dri/i965/brw_gs.c
index 9c37d96..a898260 100644
--- a/src/mesa/drivers/dri/i965/brw_gs.c
+++ b/src/mesa/drivers/dri/i965/brw_gs.c
@@ -191,7 +191,7 @@ brw_codegen_gs_prog(struct brw_context *brw,
key, sizeof(*key),
program, program_size,
&prog_data, sizeof(prog_data),
- &stage_state->prog_offset, &brw->gs.prog_data);
+ &stage_state->prog_offset, &brw->gs.base.prog_data);
ralloc_free(mem_ctx);
return true;
@@ -248,7 +248,6 @@ brw_upload_gs_prog(struct brw_context *brw)
/* Other state atoms had better not try to access prog_data, since
* there's no GS program.
*/
- brw->gs.prog_data = NULL;
brw->gs.base.prog_data = NULL;
return;
@@ -258,13 +257,13 @@ brw_upload_gs_prog(struct brw_context *brw)
if (!brw_search_cache(&brw->cache, BRW_CACHE_GS_PROG,
&key, sizeof(key),
- &stage_state->prog_offset, &brw->gs.prog_data)) {
+ &stage_state->prog_offset,
+ &brw->gs.base.prog_data)) {
bool success = brw_codegen_gs_prog(brw, current[MESA_SHADER_GEOMETRY],
gp, &key);
assert(success);
(void)success;
}
- brw->gs.base.prog_data = &brw->gs.prog_data->base.base;
}
bool
@@ -275,7 +274,7 @@ brw_gs_precompile(struct gl_context *ctx,
struct brw_context *brw = brw_context(ctx);
struct brw_gs_prog_key key;
uint32_t old_prog_offset = brw->gs.base.prog_offset;
- struct brw_gs_prog_data *old_prog_data = brw->gs.prog_data;
+ struct brw_stage_prog_data *old_prog_data = brw->gs.base.prog_data;
bool success;
struct gl_geometry_program *gp = (struct gl_geometry_program *) prog;
@@ -289,7 +288,7 @@ brw_gs_precompile(struct gl_context *ctx,
success = brw_codegen_gs_prog(brw, shader_prog, bgp, &key);
brw->gs.base.prog_offset = old_prog_offset;
- brw->gs.prog_data = old_prog_data;
+ brw->gs.base.prog_data = old_prog_data;
return success;
}
diff --git a/src/mesa/drivers/dri/i965/brw_gs_surface_state.c
b/src/mesa/drivers/dri/i965/brw_gs_surface_state.c
index f41b449..371255c 100644
--- a/src/mesa/drivers/dri/i965/brw_gs_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_gs_surface_state.c
@@ -48,12 +48,12 @@ brw_upload_gs_pull_constants(struct brw_context *brw)
return;
/* BRW_NEW_GS_PROG_DATA */
- const struct brw_vue_prog_data *prog_data = &brw->gs.prog_data->base;
+ const struct brw_stage_prog_data *prog_data = brw->gs.base.prog_data;
_mesa_shader_write_subroutine_indices(&brw->ctx, MESA_SHADER_GEOMETRY);
/* _NEW_PROGRAM_CONSTANTS */
brw_upload_pull_constants(brw, BRW_NEW_GS_CONSTBUF, &gp->program.Base,
- stage_state, &prog_data->base);
+ stage_state, prog_data);
}
const struct brw_tracked_state brw_gs_pull_constants = {
@@ -80,10 +80,10 @@ brw_upload_gs_ubo_surfaces(struct brw_context *brw)
return;
/* BRW_NEW_GS_PROG_DATA */
- struct brw_vue_prog_data *prog_data = &brw->gs.prog_data->base;
+ struct brw_stage_prog_data *prog_data = brw->gs.base.prog_data;
brw_upload_ubo_surfaces(brw, prog->_LinkedShaders[MESA_SHADER_GEOMETRY],
- &brw->gs.base, &prog_data->base);
+ &brw->gs.base, prog_data);
}
const struct brw_tracked_state brw_gs_ubo_surfaces = {
@@ -108,7 +108,7 @@ brw_upload_gs_abo_surfaces(struct brw_context *brw)
if (prog) {
/* BRW_NEW_GS_PROG_DATA */
brw_upload_abo_surfaces(brw, prog->_LinkedShaders[MESA_SHADER_GEOMETRY],
- &brw->gs.base, &brw->gs.prog_data->base.base);
+ &brw->gs.base, brw->gs.base.prog_data);
}
}
@@ -134,7 +134,7 @@ brw_upload_gs_image_surfaces(struct brw_context *brw)
if (prog) {
/* BRW_NEW_GS_PROG_DATA, BRW_NEW_IMAGE_UNITS, _NEW_TEXTURE */
brw_upload_image_surfaces(brw,
prog->_LinkedShaders[MESA_SHADER_GEOMETRY],
- &brw->gs.base, &brw->gs.prog_data->base.base);
+ &brw->gs.base, brw->gs.base.prog_data);
}
}
diff --git a/src/mesa/drivers/dri/i965/brw_state_cache.c
b/src/mesa/drivers/dri/i965/brw_state_cache.c
index 9e33182..ad716d2 100644
--- a/src/mesa/drivers/dri/i965/brw_state_cache.c
+++ b/src/mesa/drivers/dri/i965/brw_state_cache.c
@@ -401,7 +401,6 @@ brw_clear_cache(struct brw_context *brw, struct brw_cache
*cache)
brw->vs.base.prog_data = NULL;
brw->tcs.base.prog_data = NULL;
brw->tes.base.prog_data = NULL;
- brw->gs.prog_data = NULL;
brw->gs.base.prog_data = NULL;
brw->wm.prog_data = NULL;
brw->wm.base.prog_data = NULL;
diff --git a/src/mesa/drivers/dri/i965/gen6_clip_state.c
b/src/mesa/drivers/dri/i965/gen6_clip_state.c
index 33d4f5a..22ca8d4 100644
--- a/src/mesa/drivers/dri/i965/gen6_clip_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_clip_state.c
@@ -43,9 +43,10 @@ brw_is_drawing_points(const struct brw_context *brw)
return true;
}
- if (brw->gs.prog_data) {
+ if (brw->gs.base.prog_data) {
/* BRW_NEW_GS_PROG_DATA */
- return brw->gs.prog_data->output_topology == _3DPRIM_POINTLIST;
+ return brw_gs_prog_data(brw->gs.base.prog_data)->output_topology ==
+ _3DPRIM_POINTLIST;
} else if (brw->tes.base.prog_data) {
/* BRW_NEW_TES_PROG_DATA */
return brw_tes_prog_data(brw->tes.base.prog_data)->output_topology ==
@@ -66,9 +67,10 @@ brw_is_drawing_lines(const struct brw_context *brw)
return true;
}
- if (brw->gs.prog_data) {
+ if (brw->gs.base.prog_data) {
/* BRW_NEW_GS_PROG_DATA */
- return brw->gs.prog_data->output_topology == _3DPRIM_LINESTRIP;
+ return brw_gs_prog_data(brw->gs.base.prog_data)->output_topology ==
+ _3DPRIM_LINESTRIP;
} else if (brw->tes.base.prog_data) {
/* BRW_NEW_TES_PROG_DATA */
return brw_tes_prog_data(brw->tes.base.prog_data)->output_topology ==
diff --git a/src/mesa/drivers/dri/i965/gen6_gs_state.c
b/src/mesa/drivers/dri/i965/gen6_gs_state.c
index 2a16d22..ca212c8 100644
--- a/src/mesa/drivers/dri/i965/gen6_gs_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_gs_state.c
@@ -42,7 +42,7 @@ gen6_upload_gs_push_constants(struct brw_context *brw)
if (gp) {
/* BRW_NEW_GS_PROG_DATA */
- struct brw_stage_prog_data *prog_data = &brw->gs.prog_data->base.base;
+ struct brw_stage_prog_data *prog_data = brw->gs.base.prog_data;
_mesa_shader_write_subroutine_indices(&brw->ctx, MESA_SHADER_GEOMETRY);
gen6_upload_push_constants(brw, &gp->program.Base, prog_data,
@@ -97,8 +97,12 @@ upload_gs_state(struct brw_context *brw)
/* BRW_NEW_GEOMETRY_PROGRAM */
bool active = brw->geometry_program;
/* BRW_NEW_GS_PROG_DATA */
- const struct brw_vue_prog_data *prog_data = &brw->gs.prog_data->base;
const struct brw_stage_state *stage_state = &brw->gs.base;
+ const struct brw_stage_prog_data *prog_data = stage_state->prog_data;
+ const struct brw_vue_prog_data *vue_prog_data =
+ brw_vue_prog_data(stage_state->prog_data);
+ const struct brw_gs_prog_data *gs_prog_data =
+ brw_gs_prog_data(stage_state->prog_data);
if (!active || stage_state->push_const_size == 0) {
/* Disable the push constant buffers. */
@@ -139,10 +143,10 @@ upload_gs_state(struct brw_context *brw)
OUT_BATCH(GEN6_GS_SPF_MODE | GEN6_GS_VECTOR_MASK_ENABLE |
((ALIGN(stage_state->sampler_count, 4)/4) <<
GEN6_GS_SAMPLER_COUNT_SHIFT) |
- ((prog_data->base.binding_table.size_bytes / 4) <<
+ ((prog_data->binding_table.size_bytes / 4) <<
GEN6_GS_BINDING_TABLE_ENTRY_COUNT_SHIFT));
- if (prog_data->base.total_scratch) {
+ if (prog_data->total_scratch) {
OUT_RELOC(stage_state->scratch_bo,
I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
ffs(stage_state->per_thread_scratch) - 11);
@@ -150,10 +154,10 @@ upload_gs_state(struct brw_context *brw)
OUT_BATCH(0); /* no scratch space */
}
- OUT_BATCH((prog_data->urb_read_length <<
+ OUT_BATCH((vue_prog_data->urb_read_length <<
GEN6_GS_URB_READ_LENGTH_SHIFT) |
(0 << GEN6_GS_URB_ENTRY_READ_OFFSET_SHIFT) |
- (prog_data->base.dispatch_grf_start_reg <<
+ (prog_data->dispatch_grf_start_reg <<
GEN6_GS_DISPATCH_START_GRF_SHIFT));
OUT_BATCH(((devinfo->max_gs_threads - 1) << GEN6_GS_MAX_THREADS_SHIFT) |
@@ -161,7 +165,7 @@ upload_gs_state(struct brw_context *brw)
GEN6_GS_SO_STATISTICS_ENABLE |
GEN6_GS_RENDERING_ENABLE);
- if (brw->gs.prog_data->gen6_xfb_enabled) {
+ if (gs_prog_data->gen6_xfb_enabled) {
/* GEN6_GS_REORDER is equivalent to GEN7_GS_REORDER_TRAILING
* in gen7. SNB and IVB specs are the same regarding the reordering of
* TRISTRIP/TRISTRIP_REV vertices and triangle orientation, so we do
diff --git a/src/mesa/drivers/dri/i965/gen6_urb.c
b/src/mesa/drivers/dri/i965/gen6_urb.c
index c3dcf7d..3658c38 100644
--- a/src/mesa/drivers/dri/i965/gen6_urb.c
+++ b/src/mesa/drivers/dri/i965/gen6_urb.c
@@ -128,7 +128,9 @@ upload_urb(struct brw_context *brw)
*/
unsigned gs_size = vs_size;
if (brw->geometry_program) {
- gs_size = brw->gs.prog_data->base.urb_entry_size;
+ const struct brw_vue_prog_data *gs_vue_prog_data =
+ brw_vue_prog_data(brw->gs.base.prog_data);
+ gs_size = gs_vue_prog_data->urb_entry_size;
assert(gs_size >= 1);
}
diff --git a/src/mesa/drivers/dri/i965/gen7_gs_state.c
b/src/mesa/drivers/dri/i965/gen7_gs_state.c
index 90abe3e..899c058 100644
--- a/src/mesa/drivers/dri/i965/gen7_gs_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_gs_state.c
@@ -36,7 +36,11 @@ upload_gs_state(struct brw_context *brw)
/* BRW_NEW_GEOMETRY_PROGRAM */
bool active = brw->geometry_program;
/* BRW_NEW_GS_PROG_DATA */
- const struct brw_vue_prog_data *prog_data = &brw->gs.prog_data->base;
+ const struct brw_stage_prog_data *prog_data = stage_state->prog_data;
+ const struct brw_vue_prog_data *vue_prog_data =
+ brw_vue_prog_data(stage_state->prog_data);
+ const struct brw_gs_prog_data *gs_prog_data =
+ brw_gs_prog_data(stage_state->prog_data);
/**
* From Graphics BSpec: 3D-Media-GPGPU Engine > 3D Pipeline Stages >
@@ -59,10 +63,10 @@ upload_gs_state(struct brw_context *brw)
OUT_BATCH(stage_state->prog_offset);
OUT_BATCH(((ALIGN(stage_state->sampler_count, 4)/4) <<
GEN6_GS_SAMPLER_COUNT_SHIFT) |
- ((brw->gs.prog_data->base.base.binding_table.size_bytes / 4) <<
+ ((prog_data->binding_table.size_bytes / 4) <<
GEN6_GS_BINDING_TABLE_ENTRY_COUNT_SHIFT));
- if (brw->gs.prog_data->base.base.total_scratch) {
+ if (prog_data->total_scratch) {
OUT_RELOC(stage_state->scratch_bo,
I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
ffs(stage_state->per_thread_scratch) - 11);
@@ -71,14 +75,13 @@ upload_gs_state(struct brw_context *brw)
}
uint32_t dw4 =
- ((brw->gs.prog_data->output_vertex_size_hwords * 2 - 1) <<
+ ((gs_prog_data->output_vertex_size_hwords * 2 - 1) <<
GEN7_GS_OUTPUT_VERTEX_SIZE_SHIFT) |
- (brw->gs.prog_data->output_topology <<
- GEN7_GS_OUTPUT_TOPOLOGY_SHIFT) |
- (prog_data->urb_read_length <<
+ (gs_prog_data->output_topology << GEN7_GS_OUTPUT_TOPOLOGY_SHIFT) |
+ (vue_prog_data->urb_read_length <<
GEN6_GS_URB_READ_LENGTH_SHIFT) |
(0 << GEN6_GS_URB_ENTRY_READ_OFFSET_SHIFT) |
- (prog_data->base.dispatch_grf_start_reg <<
+ (prog_data->dispatch_grf_start_reg <<
GEN6_GS_DISPATCH_START_GRF_SHIFT);
/* Note: the meaning of the GEN7_GS_REORDER_TRAILING bit changes between
@@ -109,23 +112,23 @@ upload_gs_state(struct brw_context *brw)
*/
uint32_t dw5 =
((devinfo->max_gs_threads - 1) << max_threads_shift) |
- (brw->gs.prog_data->control_data_header_size_hwords <<
+ (gs_prog_data->control_data_header_size_hwords <<
GEN7_GS_CONTROL_DATA_HEADER_SIZE_SHIFT) |
- ((brw->gs.prog_data->invocations - 1) <<
+ ((gs_prog_data->invocations - 1) <<
GEN7_GS_INSTANCE_CONTROL_SHIFT) |
- SET_FIELD(prog_data->dispatch_mode, GEN7_GS_DISPATCH_MODE) |
+ SET_FIELD(vue_prog_data->dispatch_mode, GEN7_GS_DISPATCH_MODE) |
GEN6_GS_STATISTICS_ENABLE |
- (brw->gs.prog_data->include_primitive_id ?
+ (gs_prog_data->include_primitive_id ?
GEN7_GS_INCLUDE_PRIMITIVE_ID : 0) |
GEN7_GS_REORDER_TRAILING |
GEN7_GS_ENABLE;
uint32_t dw6 = 0;
if (brw->is_haswell) {
- dw6 |= brw->gs.prog_data->control_data_format <<
+ dw6 |= gs_prog_data->control_data_format <<
HSW_GS_CONTROL_DATA_FORMAT_SHIFT;
} else {
- dw5 |= brw->gs.prog_data->control_data_format <<
+ dw5 |= gs_prog_data->control_data_format <<
IVB_GS_CONTROL_DATA_FORMAT_SHIFT;
}
diff --git a/src/mesa/drivers/dri/i965/gen7_urb.c
b/src/mesa/drivers/dri/i965/gen7_urb.c
index 2991cda..c4b0e73 100644
--- a/src/mesa/drivers/dri/i965/gen7_urb.c
+++ b/src/mesa/drivers/dri/i965/gen7_urb.c
@@ -211,7 +211,9 @@ gen7_upload_urb(struct brw_context *brw, unsigned vs_size,
/* BRW_NEW_VS_PROG_DATA */
unsigned vs_entry_size_bytes = vs_size * 64;
/* BRW_NEW_GEOMETRY_PROGRAM, BRW_NEW_GS_PROG_DATA */
- unsigned gs_size = gs_present ? brw->gs.prog_data->base.urb_entry_size : 1;
+ const struct brw_vue_prog_data *gs_vue_prog_data =
+ brw_vue_prog_data(brw->gs.base.prog_data);
+ unsigned gs_size = gs_present ? gs_vue_prog_data->urb_entry_size : 1;
unsigned gs_entry_size_bytes = gs_size * 64;
/* BRW_NEW_TCS_PROG_DATA */
diff --git a/src/mesa/drivers/dri/i965/gen8_gs_state.c
b/src/mesa/drivers/dri/i965/gen8_gs_state.c
index 5838bc8..935e8ac 100644
--- a/src/mesa/drivers/dri/i965/gen8_gs_state.c
+++ b/src/mesa/drivers/dri/i965/gen8_gs_state.c
@@ -34,12 +34,16 @@ gen8_upload_gs_state(struct brw_context *brw)
/* BRW_NEW_GEOMETRY_PROGRAM */
bool active = brw->geometry_program;
/* BRW_NEW_GS_PROG_DATA */
- const struct brw_vue_prog_data *prog_data = &brw->gs.prog_data->base;
+ const struct brw_stage_prog_data *prog_data = stage_state->prog_data;
+ const struct brw_vue_prog_data *vue_prog_data =
+ brw_vue_prog_data(stage_state->prog_data);
+ const struct brw_gs_prog_data *gs_prog_data =
+ brw_gs_prog_data(stage_state->prog_data);
if (active) {
int urb_entry_write_offset = 1;
uint32_t urb_entry_output_length =
- ((prog_data->vue_map.num_slots + 1) / 2 - urb_entry_write_offset);
+ ((vue_prog_data->vue_map.num_slots + 1) / 2 - urb_entry_write_offset);
if (urb_entry_output_length == 0)
urb_entry_output_length = 1;
@@ -48,13 +52,13 @@ gen8_upload_gs_state(struct brw_context *brw)
OUT_BATCH(_3DSTATE_GS << 16 | (10 - 2));
OUT_BATCH(stage_state->prog_offset);
OUT_BATCH(0);
- OUT_BATCH(brw->gs.prog_data->vertices_in |
+ OUT_BATCH(gs_prog_data->vertices_in |
((ALIGN(stage_state->sampler_count, 4)/4) <<
GEN6_GS_SAMPLER_COUNT_SHIFT) |
- ((prog_data->base.binding_table.size_bytes / 4) <<
+ ((prog_data->binding_table.size_bytes / 4) <<
GEN6_GS_BINDING_TABLE_ENTRY_COUNT_SHIFT));
- if (brw->gs.prog_data->base.base.total_scratch) {
+ if (prog_data->total_scratch) {
OUT_RELOC64(stage_state->scratch_bo,
I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
ffs(stage_state->per_thread_scratch) - 11);
@@ -64,35 +68,35 @@ gen8_upload_gs_state(struct brw_context *brw)
}
/* DW6 */
- OUT_BATCH(((brw->gs.prog_data->output_vertex_size_hwords * 2 - 1) <<
+ OUT_BATCH(((gs_prog_data->output_vertex_size_hwords * 2 - 1) <<
GEN7_GS_OUTPUT_VERTEX_SIZE_SHIFT) |
- (brw->gs.prog_data->output_topology <<
+ (gs_prog_data->output_topology <<
GEN7_GS_OUTPUT_TOPOLOGY_SHIFT) |
- (prog_data->include_vue_handles ?
+ (vue_prog_data->include_vue_handles ?
GEN7_GS_INCLUDE_VERTEX_HANDLES : 0) |
- (prog_data->urb_read_length <<
+ (vue_prog_data->urb_read_length <<
GEN6_GS_URB_READ_LENGTH_SHIFT) |
(0 << GEN6_GS_URB_ENTRY_READ_OFFSET_SHIFT) |
- (prog_data->base.dispatch_grf_start_reg <<
+ (prog_data->dispatch_grf_start_reg <<
GEN6_GS_DISPATCH_START_GRF_SHIFT));
- uint32_t dw7 = (brw->gs.prog_data->control_data_header_size_hwords <<
+ uint32_t dw7 = (gs_prog_data->control_data_header_size_hwords <<
GEN7_GS_CONTROL_DATA_HEADER_SIZE_SHIFT) |
- SET_FIELD(prog_data->dispatch_mode,
+ SET_FIELD(vue_prog_data->dispatch_mode,
GEN7_GS_DISPATCH_MODE) |
- ((brw->gs.prog_data->invocations - 1) <<
+ ((gs_prog_data->invocations - 1) <<
GEN7_GS_INSTANCE_CONTROL_SHIFT) |
GEN6_GS_STATISTICS_ENABLE |
- (brw->gs.prog_data->include_primitive_id ?
+ (gs_prog_data->include_primitive_id ?
GEN7_GS_INCLUDE_PRIMITIVE_ID : 0) |
GEN7_GS_REORDER_TRAILING |
GEN7_GS_ENABLE;
- uint32_t dw8 = brw->gs.prog_data->control_data_format <<
+ uint32_t dw8 = gs_prog_data->control_data_format <<
HSW_GS_CONTROL_DATA_FORMAT_SHIFT;
- if (brw->gs.prog_data->static_vertex_count != -1) {
+ if (gs_prog_data->static_vertex_count != -1) {
dw8 |= GEN8_GS_STATIC_OUTPUT |
- SET_FIELD(brw->gs.prog_data->static_vertex_count,
+ SET_FIELD(gs_prog_data->static_vertex_count,
GEN8_GS_STATIC_VERTEX_COUNT);
}
@@ -108,7 +112,7 @@ gen8_upload_gs_state(struct brw_context *brw)
OUT_BATCH(dw8);
/* DW9 */
- OUT_BATCH(prog_data->cull_distance_mask |
+ OUT_BATCH(vue_prog_data->cull_distance_mask |
(urb_entry_output_length << GEN8_GS_URB_OUTPUT_LENGTH_SHIFT) |
(urb_entry_write_offset <<
GEN8_GS_URB_ENTRY_OUTPUT_OFFSET_SHIFT));
--
2.10.0
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