From: Marek Olšák <marek.ol...@amd.com>
Oh my god, I wonder what catastrophic issues this was causing on SI.
Cc: 13.0 <mesa-sta...@lists.freedesktop.org>
---
src/gallium/drivers/radeon/r600_texture.c | 14 +++++++-------
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/src/gallium/drivers/radeon/r600_texture.c
b/src/gallium/drivers/radeon/r600_texture.c
index 625d091..b57cc92 100644
--- a/src/gallium/drivers/radeon/r600_texture.c
+++ b/src/gallium/drivers/radeon/r600_texture.c
@@ -2435,43 +2435,43 @@ static void si_set_optimal_micro_tile_mode(struct
r600_common_screen *rscreen,
rtex->surface.tiling_index[0] = 28;
break;
default: /* depth, thick */
assert(!"unexpected micro mode");
return;
}
} else { /* SI */
switch (rtex->last_msaa_resolve_target_micro_mode) {
case 0: /* displayable */
switch (rtex->surface.bpe) {
- case 8:
+ case 1:
rtex->surface.tiling_index[0] = 10;
break;
- case 16:
+ case 2:
rtex->surface.tiling_index[0] = 11;
break;
- default: /* 32, 64 */
+ default: /* 4, 8 */
rtex->surface.tiling_index[0] = 12;
break;
}
break;
case 1: /* thin */
switch (rtex->surface.bpe) {
- case 8:
+ case 1:
rtex->surface.tiling_index[0] = 14;
break;
- case 16:
+ case 2:
rtex->surface.tiling_index[0] = 15;
break;
- case 32:
+ case 4:
rtex->surface.tiling_index[0] = 16;
break;
- default: /* 64, 128 */
+ default: /* 8, 16 */
rtex->surface.tiling_index[0] = 17;
break;
}
break;
default: /* depth, thick */
assert(!"unexpected micro mode");
return;
}
}
--
2.7.4
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