From: Marek Olšák <marek.ol...@amd.com> it has no effect whatsoever --- src/gallium/drivers/r600/evergreen_compute.c | 6 ++---- src/gallium/drivers/r600/r600_shader.c | 2 +- src/gallium/drivers/r600/r600_state_common.c | 4 ++-- src/gallium/drivers/radeon/r600_query.c | 4 ++-- src/gallium/drivers/radeon/r600_texture.c | 3 +-- src/gallium/drivers/radeon/radeon_video.c | 2 +- src/gallium/drivers/radeonsi/si_hw_context.c | 2 +- src/gallium/drivers/radeonsi/si_pipe.c | 5 ++--- src/gallium/drivers/radeonsi/si_pipe.h | 3 +-- src/gallium/drivers/radeonsi/si_pm4.c | 2 +- src/gallium/drivers/radeonsi/si_state_shaders.c | 9 ++++----- 11 files changed, 18 insertions(+), 24 deletions(-)
diff --git a/src/gallium/drivers/r600/evergreen_compute.c b/src/gallium/drivers/r600/evergreen_compute.c index fe43f37..f66c9f6 100644 --- a/src/gallium/drivers/r600/evergreen_compute.c +++ b/src/gallium/drivers/r600/evergreen_compute.c @@ -80,23 +80,21 @@ writable images will consume TEX slots, VTX slots too because of linear indexing */ struct r600_resource *r600_compute_buffer_alloc_vram(struct r600_screen *screen, unsigned size) { struct pipe_resource *buffer = NULL; assert(size); buffer = pipe_buffer_create((struct pipe_screen*) screen, - PIPE_BIND_CUSTOM, - PIPE_USAGE_IMMUTABLE, - size); + 0, PIPE_USAGE_IMMUTABLE, size); return (struct r600_resource *)buffer; } static void evergreen_set_rat(struct r600_pipe_compute *pipe, unsigned id, struct r600_resource *bo, int start, int size) @@ -328,21 +326,21 @@ static void evergreen_compute_upload_input(struct pipe_context *ctx, struct pipe_box box; struct pipe_transfer *transfer = NULL; if (shader->input_size == 0) { return; } if (!shader->kernel_param) { /* Add space for the grid dimensions */ shader->kernel_param = (struct r600_resource *) - pipe_buffer_create(ctx->screen, PIPE_BIND_CUSTOM, + pipe_buffer_create(ctx->screen, 0, PIPE_USAGE_IMMUTABLE, input_size); } u_box_1d(0, input_size, &box); num_work_groups_start = ctx->transfer_map(ctx, (struct pipe_resource*)shader->kernel_param, 0, PIPE_TRANSFER_WRITE | PIPE_TRANSFER_DISCARD_RANGE, &box, &transfer); global_size_start = num_work_groups_start + (3 * (sizeof(uint) /4)); local_size_start = global_size_start + (3 * (sizeof(uint)) / 4); diff --git a/src/gallium/drivers/r600/r600_shader.c b/src/gallium/drivers/r600/r600_shader.c index 59a13ec..b5e7b7d 100644 --- a/src/gallium/drivers/r600/r600_shader.c +++ b/src/gallium/drivers/r600/r600_shader.c @@ -130,21 +130,21 @@ static void r600_dump_streamout(struct pipe_stream_output_info *so) } static int store_shader(struct pipe_context *ctx, struct r600_pipe_shader *shader) { struct r600_context *rctx = (struct r600_context *)ctx; uint32_t *ptr, i; if (shader->bo == NULL) { shader->bo = (struct r600_resource*) - pipe_buffer_create(ctx->screen, PIPE_BIND_CUSTOM, PIPE_USAGE_IMMUTABLE, shader->shader.bc.ndw * 4); + pipe_buffer_create(ctx->screen, 0, PIPE_USAGE_IMMUTABLE, shader->shader.bc.ndw * 4); if (shader->bo == NULL) { return -ENOMEM; } ptr = r600_buffer_map_sync_with_rings(&rctx->b, shader->bo, PIPE_TRANSFER_WRITE); if (R600_BIG_ENDIAN) { for (i = 0; i < shader->shader.bc.ndw; ++i) { ptr[i] = util_cpu_to_le32(shader->shader.bc.bytecode[i]); } } else { memcpy(ptr, shader->shader.bc.bytecode, shader->shader.bc.ndw * sizeof(*ptr)); diff --git a/src/gallium/drivers/r600/r600_state_common.c b/src/gallium/drivers/r600/r600_state_common.c index 48c5443..60490b0 100644 --- a/src/gallium/drivers/r600/r600_state_common.c +++ b/src/gallium/drivers/r600/r600_state_common.c @@ -1319,28 +1319,28 @@ static void update_gs_block_state(struct r600_context *rctx, unsigned enable) r600_mark_atom_dirty(rctx, &rctx->shader_stages.atom); } if (rctx->gs_rings.enable != enable) { rctx->gs_rings.enable = enable; r600_mark_atom_dirty(rctx, &rctx->gs_rings.atom); if (enable && !rctx->gs_rings.esgs_ring.buffer) { unsigned size = 0x1C000; rctx->gs_rings.esgs_ring.buffer = - pipe_buffer_create(rctx->b.b.screen, PIPE_BIND_CUSTOM, + pipe_buffer_create(rctx->b.b.screen, 0, PIPE_USAGE_DEFAULT, size); rctx->gs_rings.esgs_ring.buffer_size = size; size = 0x4000000; rctx->gs_rings.gsvs_ring.buffer = - pipe_buffer_create(rctx->b.b.screen, PIPE_BIND_CUSTOM, + pipe_buffer_create(rctx->b.b.screen, 0, PIPE_USAGE_DEFAULT, size); rctx->gs_rings.gsvs_ring.buffer_size = size; } if (enable) { r600_set_constant_buffer(&rctx->b.b, PIPE_SHADER_GEOMETRY, R600_GS_RING_CONST_BUFFER, &rctx->gs_rings.esgs_ring); if (rctx->tes_shader) { r600_set_constant_buffer(&rctx->b.b, PIPE_SHADER_TESS_EVAL, R600_GS_RING_CONST_BUFFER, &rctx->gs_rings.gsvs_ring); diff --git a/src/gallium/drivers/radeon/r600_query.c b/src/gallium/drivers/radeon/r600_query.c index a5c8595..047f597 100644 --- a/src/gallium/drivers/radeon/r600_query.c +++ b/src/gallium/drivers/radeon/r600_query.c @@ -331,21 +331,21 @@ static struct r600_resource *r600_new_query_buffer(struct r600_common_context *c struct r600_query_hw *query) { unsigned buf_size = MAX2(query->result_size, ctx->screen->info.min_alloc_size); /* Queries are normally read by the CPU after * being written by the gpu, hence staging is probably a good * usage pattern. */ struct r600_resource *buf = (struct r600_resource*) - pipe_buffer_create(ctx->b.screen, PIPE_BIND_CUSTOM, + pipe_buffer_create(ctx->b.screen, 0, PIPE_USAGE_STAGING, buf_size); if (!buf) return NULL; if (!query->ops->prepare_buffer(ctx, query, buf)) { r600_resource_reference(&buf, NULL); return NULL; } return buf; @@ -1573,21 +1573,21 @@ void r600_query_init_backend_mask(struct r600_common_context *ctx) if (mask != 0) { ctx->backend_mask = mask; return; } } /* otherwise backup path for older kernels */ /* create buffer for event data */ buffer = (struct r600_resource*) - pipe_buffer_create(ctx->b.screen, PIPE_BIND_CUSTOM, + pipe_buffer_create(ctx->b.screen, 0, PIPE_USAGE_STAGING, ctx->max_db*16); if (!buffer) goto err; /* initialize buffer with zeroes */ results = r600_buffer_map_sync_with_rings(ctx, buffer, PIPE_TRANSFER_WRITE); if (results) { memset(results, 0, ctx->max_db * 4 * 4); /* emit EVENT_WRITE for ZPASS_DONE */ diff --git a/src/gallium/drivers/radeon/r600_texture.c b/src/gallium/drivers/radeon/r600_texture.c index db65cd9..bc981da 100644 --- a/src/gallium/drivers/radeon/r600_texture.c +++ b/src/gallium/drivers/radeon/r600_texture.c @@ -872,22 +872,21 @@ static void r600_texture_allocate_htile(struct r600_common_screen *rscreen, clear_value = 0x0000030F; } else { r600_texture_get_htile_size(rscreen, rtex); clear_value = 0; } if (!rtex->surface.htile_size) return; rtex->htile_buffer = (struct r600_resource*) - r600_aligned_buffer_create(&rscreen->b, PIPE_BIND_CUSTOM, - PIPE_USAGE_DEFAULT, + r600_aligned_buffer_create(&rscreen->b, 0, PIPE_USAGE_DEFAULT, rtex->surface.htile_size, rtex->surface.htile_alignment); if (rtex->htile_buffer == NULL) { /* this is not a fatal error as we can still keep rendering * without htile buffer */ R600_ERR("Failed to create buffer object for htile buffer.\n"); } else { r600_screen_clear_buffer(rscreen, &rtex->htile_buffer->b.b, 0, rtex->surface.htile_size, clear_value, R600_COHERENCY_NONE); diff --git a/src/gallium/drivers/radeon/radeon_video.c b/src/gallium/drivers/radeon/radeon_video.c index b4fd306..59e735b 100644 --- a/src/gallium/drivers/radeon/radeon_video.c +++ b/src/gallium/drivers/radeon/radeon_video.c @@ -65,21 +65,21 @@ bool rvid_create_buffer(struct pipe_screen *screen, struct rvid_buffer *buffer, unsigned size, unsigned usage) { memset(buffer, 0, sizeof(*buffer)); buffer->usage = usage; /* Hardware buffer placement restrictions require the kernel to be * able to move buffers around individually, so request a * non-sub-allocated buffer. */ buffer->res = (struct r600_resource *) - pipe_buffer_create(screen, PIPE_BIND_CUSTOM | PIPE_BIND_SHARED, + pipe_buffer_create(screen, PIPE_BIND_SHARED, usage, size); return buffer->res != NULL; } /* destroy a buffer */ void rvid_destroy_buffer(struct rvid_buffer *buffer) { r600_resource_reference(&buffer->res, NULL); } diff --git a/src/gallium/drivers/radeonsi/si_hw_context.c b/src/gallium/drivers/radeonsi/si_hw_context.c index 7c11baf..87ba316 100644 --- a/src/gallium/drivers/radeonsi/si_hw_context.c +++ b/src/gallium/drivers/radeonsi/si_hw_context.c @@ -152,21 +152,21 @@ void si_context_gfx_flush(void *context, unsigned flags, } void si_begin_new_cs(struct si_context *ctx) { if (ctx->is_debug) { uint32_t zero = 0; /* Create a buffer used for writing trace IDs and initialize it to 0. */ assert(!ctx->trace_buf); ctx->trace_buf = (struct r600_resource*) - pipe_buffer_create(ctx->b.b.screen, PIPE_BIND_CUSTOM, + pipe_buffer_create(ctx->b.b.screen, 0, PIPE_USAGE_STAGING, 4); if (ctx->trace_buf) pipe_buffer_write_nooverlap(&ctx->b.b, &ctx->trace_buf->b.b, 0, sizeof(zero), &zero); ctx->trace_id = 0; } if (ctx->trace_buf) si_trace_emit(ctx); diff --git a/src/gallium/drivers/radeonsi/si_pipe.c b/src/gallium/drivers/radeonsi/si_pipe.c index ccd7f3f..bf3b442 100644 --- a/src/gallium/drivers/radeonsi/si_pipe.c +++ b/src/gallium/drivers/radeonsi/si_pipe.c @@ -195,36 +195,35 @@ static struct pipe_context *si_create_context(struct pipe_screen *screen, if (ws->cs_add_const_preamble_ib) { sctx->ce_preamble_ib = ws->cs_add_const_preamble_ib(sctx->b.gfx.cs); if (!sctx->ce_preamble_ib) goto fail; } sctx->ce_suballocator = u_suballocator_create(&sctx->b.b, 1024 * 1024, - PIPE_BIND_CUSTOM, - PIPE_USAGE_DEFAULT, false); + 0, PIPE_USAGE_DEFAULT, false); if (!sctx->ce_suballocator) goto fail; } sctx->b.gfx.flush = si_context_gfx_flush; /* Border colors. */ sctx->border_color_table = malloc(SI_MAX_BORDER_COLORS * sizeof(*sctx->border_color_table)); if (!sctx->border_color_table) goto fail; sctx->border_color_buffer = (struct r600_resource*) - pipe_buffer_create(screen, PIPE_BIND_CUSTOM, PIPE_USAGE_DEFAULT, + pipe_buffer_create(screen, 0, PIPE_USAGE_DEFAULT, SI_MAX_BORDER_COLORS * sizeof(*sctx->border_color_table)); if (!sctx->border_color_buffer) goto fail; sctx->border_color_map = ws->buffer_map(sctx->border_color_buffer->buf, NULL, PIPE_TRANSFER_WRITE); if (!sctx->border_color_map) goto fail; diff --git a/src/gallium/drivers/radeonsi/si_pipe.h b/src/gallium/drivers/radeonsi/si_pipe.h index 8fc5fcc..6b74e49 100644 --- a/src/gallium/drivers/radeonsi/si_pipe.h +++ b/src/gallium/drivers/radeonsi/si_pipe.h @@ -399,22 +399,21 @@ struct pipe_video_buffer *si_video_buffer_create(struct pipe_context *pipe, /* * common helpers */ static inline struct r600_resource * si_resource_create_custom(struct pipe_screen *screen, unsigned usage, unsigned size) { assert(size); - return r600_resource(pipe_buffer_create(screen, - PIPE_BIND_CUSTOM, usage, size)); + return r600_resource(pipe_buffer_create(screen, 0, usage, size)); } static inline void si_invalidate_draw_sh_constants(struct si_context *sctx) { sctx->last_base_vertex = SI_BASE_VERTEX_UNKNOWN; } static inline void si_set_atom_dirty(struct si_context *sctx, diff --git a/src/gallium/drivers/radeonsi/si_pm4.c b/src/gallium/drivers/radeonsi/si_pm4.c index 386d093..97b6799 100644 --- a/src/gallium/drivers/radeonsi/si_pm4.c +++ b/src/gallium/drivers/radeonsi/si_pm4.c @@ -183,21 +183,21 @@ void si_pm4_upload_indirect_buffer(struct si_context *sctx, /* only supported on CIK and later */ if (sctx->b.chip_class < CIK) return; assert(state->ndw); assert(aligned_ndw <= SI_PM4_MAX_DW); r600_resource_reference(&state->indirect_buffer, NULL); state->indirect_buffer = (struct r600_resource*) - pipe_buffer_create(screen, PIPE_BIND_CUSTOM, + pipe_buffer_create(screen, 0, PIPE_USAGE_DEFAULT, aligned_ndw * 4); if (!state->indirect_buffer) return; /* Pad the IB to 8 DWs to meet CP fetch alignment requirements. */ if (sctx->screen->b.info.gfx_ib_pad_with_type2) { for (int i = state->ndw; i < aligned_ndw; i++) state->pm4[i] = 0x80000000; /* type2 nop packet */ } else { for (int i = state->ndw; i < aligned_ndw; i++) diff --git a/src/gallium/drivers/radeonsi/si_state_shaders.c b/src/gallium/drivers/radeonsi/si_state_shaders.c index f59bfcd..3037a04 100644 --- a/src/gallium/drivers/radeonsi/si_state_shaders.c +++ b/src/gallium/drivers/radeonsi/si_state_shaders.c @@ -1723,30 +1723,30 @@ static bool si_update_gs_ring_buffers(struct si_context *sctx) sctx->esgs_ring->width0 < esgs_ring_size); bool update_gsvs = gsvs_ring_size && (!sctx->gsvs_ring || sctx->gsvs_ring->width0 < gsvs_ring_size); if (!update_esgs && !update_gsvs) return true; if (update_esgs) { pipe_resource_reference(&sctx->esgs_ring, NULL); - sctx->esgs_ring = pipe_buffer_create(sctx->b.b.screen, PIPE_BIND_CUSTOM, + sctx->esgs_ring = pipe_buffer_create(sctx->b.b.screen, 0, PIPE_USAGE_DEFAULT, esgs_ring_size); if (!sctx->esgs_ring) return false; } if (update_gsvs) { pipe_resource_reference(&sctx->gsvs_ring, NULL); - sctx->gsvs_ring = pipe_buffer_create(sctx->b.b.screen, PIPE_BIND_CUSTOM, + sctx->gsvs_ring = pipe_buffer_create(sctx->b.b.screen, 0, PIPE_USAGE_DEFAULT, gsvs_ring_size); if (!sctx->gsvs_ring) return false; } /* Create the "init_config_gs_rings" state. */ pm4 = CALLOC_STRUCT(si_pm4_state); if (!pm4) return false; @@ -2001,30 +2001,29 @@ static void si_init_tess_factor_ring(struct si_context *sctx) case CIK: max_offchip_buffers = MIN2(max_offchip_buffers, 508); break; case VI: default: max_offchip_buffers = MIN2(max_offchip_buffers, 512); break; } assert(!sctx->tf_ring); - sctx->tf_ring = pipe_buffer_create(sctx->b.b.screen, PIPE_BIND_CUSTOM, + sctx->tf_ring = pipe_buffer_create(sctx->b.b.screen, 0, PIPE_USAGE_DEFAULT, 32768 * sctx->screen->b.info.max_se); if (!sctx->tf_ring) return; assert(((sctx->tf_ring->width0 / 4) & C_030938_SIZE) == 0); - sctx->tess_offchip_ring = pipe_buffer_create(sctx->b.b.screen, - PIPE_BIND_CUSTOM, + sctx->tess_offchip_ring = pipe_buffer_create(sctx->b.b.screen, 0, PIPE_USAGE_DEFAULT, max_offchip_buffers * sctx->screen->tess_offchip_block_dw_size * 4); if (!sctx->tess_offchip_ring) return; si_init_config_add_vgt_flush(sctx); /* Append these registers to the init config state. */ if (sctx->b.chip_class >= CIK) { -- 2.7.4 _______________________________________________ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev