Ported from radeonsi.
Note that si_make_texture_descriptor() already sets img7 to the mask
value referred to in the comment.
---
src/amd/common/ac_nir_to_llvm.c | 31 +++++++++++++++++++++++++++++++
src/amd/vulkan/radv_device.c | 11 ++---------
2 files changed, 33 insertions(+), 9 deletions(-)
diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index c68cb9c..06645be 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -3151,6 +3151,35 @@ static void set_tex_fetch_args(struct
nir_to_llvm_context *ctx,
tinfo->arg_count = num_args;
}
+/* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
+ *
+ * SI-CI:
+ * If BASE_LEVEL == LAST_LEVEL, the shader must disable anisotropic
+ * filtering manually. The driver sets img7 to a mask clearing
+ * MAX_ANISO_RATIO if BASE_LEVEL == LAST_LEVEL. The shader must do:
+ * s_and_b32 samp0, samp0, img7
+ *
+ * VI:
+ * The ANISO_OVERRIDE sampler field enables this fix in TA.
+ */
+static LLVMValueRef sici_fix_sampler_aniso(struct nir_to_llvm_context *ctx,
+ LLVMValueRef res, LLVMValueRef samp)
+{
+ LLVMBuilderRef builder = ctx->builder;
+ LLVMValueRef img7, samp0;
+
+ if (ctx->options->chip_class >= VI)
+ return samp;
+
+ img7 = LLVMBuildExtractElement(builder, res,
+ LLVMConstInt(ctx->i32, 7, 0), "");
+ samp0 = LLVMBuildExtractElement(builder, samp,
+ LLVMConstInt(ctx->i32, 0, 0), "");
+ samp0 = LLVMBuildAnd(builder, samp0, img7, "");
+ return LLVMBuildInsertElement(builder, samp, samp0,
+ LLVMConstInt(ctx->i32, 0, 0), "");
+}
+
static void tex_fetch_ptrs(struct nir_to_llvm_context *ctx,
nir_tex_instr *instr,
LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr,
@@ -3165,6 +3194,8 @@ static void tex_fetch_ptrs(struct nir_to_llvm_context
*ctx,
*samp_ptr = get_sampler_desc(ctx, instr->sampler,
DESC_SAMPLER);
else
*samp_ptr = get_sampler_desc(ctx, instr->texture,
DESC_SAMPLER);
+ if (instr->sampler_dim < GLSL_SAMPLER_DIM_RECT)
+ *samp_ptr = sici_fix_sampler_aniso(ctx, *res_ptr,
*samp_ptr);
}
if (fmask_ptr && !instr->sampler && (instr->op == nir_texop_txf_ms ||
instr->op ==
nir_texop_samples_identical))
diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index 00f3a07..70c94e9 100644
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -371,7 +371,7 @@ void radv_GetPhysicalDeviceFeatures(
.largePoints = true,
.alphaToOne = true,
.multiViewport = false,
- .samplerAnisotropy = false, /* FINISHME
*/
+ .samplerAnisotropy = true,
.textureCompressionETC2 = false,
.textureCompressionASTC_LDR = false,
.textureCompressionBC = true,
@@ -1805,14 +1805,7 @@ radv_init_sampler(struct radv_device *device,
uint32_t max_aniso = pCreateInfo->anisotropyEnable &&
pCreateInfo->maxAnisotropy > 1.0 ?
(uint32_t) pCreateInfo->maxAnisotropy :
0;
uint32_t max_aniso_ratio = radv_tex_aniso_filter(max_aniso);
- bool is_vi;
- is_vi = (device->instance->physicalDevice.rad_info.chip_class >= VI);
-
- if (!is_vi && max_aniso > 0) {
- radv_finishme("Anisotropic filtering must be disabled manually "
- "by the shader on SI-CI when BASE_LEVEL ==
LAST_LEVEL\n");
- max_aniso = max_aniso_ratio = 0;
- }
+ bool is_vi = (device->instance->physicalDevice.rad_info.chip_class >=
VI);
sampler->state[0] =
(S_008F30_CLAMP_X(radv_tex_wrap(pCreateInfo->addressModeU)) |
S_008F30_CLAMP_Y(radv_tex_wrap(pCreateInfo->addressModeV)) |
--
2.1.4
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