v2: Make intel_miptree_resolve_color() take start layer and
layer count.
Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com>
---
src/mesa/drivers/dri/i965/brw_blorp.c | 13 ++++++-----
src/mesa/drivers/dri/i965/brw_blorp.h | 3 ++-
src/mesa/drivers/dri/i965/brw_context.c | 14 +++++++-----
src/mesa/drivers/dri/i965/intel_blit.c | 4 ++--
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 32 ++++++++++++++++++++++++---
src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 3 ++-
6 files changed, 51 insertions(+), 18 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c
b/src/mesa/drivers/dri/i965/brw_blorp.c
index 556f2c0..8020a95 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.c
+++ b/src/mesa/drivers/dri/i965/brw_blorp.c
@@ -213,7 +213,8 @@ blorp_surf_for_miptree(struct brw_context *brw,
if (safe_aux_usage & (1 << ISL_AUX_USAGE_CCS_E))
flags |= INTEL_MIPTREE_IGNORE_CCS_E;
- intel_miptree_resolve_color(brw, mt, flags);
+ intel_miptree_resolve_color(brw, mt,
+ *level, start_layer, num_layers, flags);
assert(mt->fast_clear_state == INTEL_FAST_CLEAR_STATE_RESOLVED);
surf->aux_usage = ISL_AUX_USAGE_NONE;
@@ -929,19 +930,19 @@ brw_blorp_clear_color(struct brw_context *brw, struct
gl_framebuffer *fb,
}
void
-brw_blorp_resolve_color(struct brw_context *brw, struct intel_mipmap_tree *mt)
+brw_blorp_resolve_color(struct brw_context *brw, struct intel_mipmap_tree *mt,
+ unsigned level, unsigned layer)
{
- DBG("%s to mt %p\n", __FUNCTION__, mt);
+ DBG("%s to mt %p level %u layer %u\n", __FUNCTION__, mt, level, layer);
const mesa_format format = _mesa_get_srgb_format_linear(mt->format);
struct isl_surf isl_tmp[2];
struct blorp_surf surf;
- unsigned level = 0;
blorp_surf_for_miptree(brw, &surf, mt, true,
(1 << ISL_AUX_USAGE_CCS_E) |
(1 << ISL_AUX_USAGE_CCS_D),
- &level, 0 /* start_layer */, 1 /* num_layers */,
+ &level, layer, 1 /* num_layers */,
isl_tmp);
enum blorp_fast_clear_op resolve_op;
@@ -958,7 +959,7 @@ brw_blorp_resolve_color(struct brw_context *brw, struct
intel_mipmap_tree *mt)
struct blorp_batch batch;
blorp_batch_init(&brw->blorp, &batch, brw, 0);
- blorp_ccs_resolve(&batch, &surf, 0 /* level */, 0 /* layer */,
+ blorp_ccs_resolve(&batch, &surf, level, layer,
brw_blorp_to_isl_format(brw, format, true),
resolve_op);
blorp_batch_finish(&batch);
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.h
b/src/mesa/drivers/dri/i965/brw_blorp.h
index abf3956..277b00e 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.h
+++ b/src/mesa/drivers/dri/i965/brw_blorp.h
@@ -64,7 +64,8 @@ brw_blorp_clear_color(struct brw_context *brw, struct
gl_framebuffer *fb,
void
brw_blorp_resolve_color(struct brw_context *brw,
- struct intel_mipmap_tree *mt);
+ struct intel_mipmap_tree *mt,
+ unsigned level, unsigned layer);
void
intel_hiz_exec(struct brw_context *brw, struct intel_mipmap_tree *mt,
diff --git a/src/mesa/drivers/dri/i965/brw_context.c
b/src/mesa/drivers/dri/i965/brw_context.c
index 3f88f7f..6aeb12d 100644
--- a/src/mesa/drivers/dri/i965/brw_context.c
+++ b/src/mesa/drivers/dri/i965/brw_context.c
@@ -316,8 +316,9 @@ intel_update_state(struct gl_context * ctx, GLuint
new_state)
intel_renderbuffer(fb->_ColorDrawBuffers[i]);
if (irb &&
- intel_miptree_resolve_color(brw, irb->mt,
- INTEL_MIPTREE_IGNORE_CCS_E))
+ intel_miptree_resolve_color(
+ brw, irb->mt, irb->mt_level, irb->mt_layer, irb->layer_count,
+ INTEL_MIPTREE_IGNORE_CCS_E))
brw_render_cache_set_check_flush(brw, irb->mt->bo);
}
}
@@ -1349,10 +1350,13 @@ intel_resolve_for_dri2_flush(struct brw_context *brw,
rb = intel_get_renderbuffer(fb, buffers[i]);
if (rb == NULL || rb->mt == NULL)
continue;
- if (rb->mt->num_samples <= 1)
- intel_miptree_resolve_color(brw, rb->mt, 0);
- else
+ if (rb->mt->num_samples <= 1) {
+ assert(rb->mt_layer == 0 && rb->mt_level == 0 &&
+ rb->layer_count == 1);
+ intel_miptree_resolve_color(brw, rb->mt, 0, 0, 1, 0);
+ } else {
intel_renderbuffer_downsample(brw, rb);
+ }
}
}
diff --git a/src/mesa/drivers/dri/i965/intel_blit.c
b/src/mesa/drivers/dri/i965/intel_blit.c
index 7e97fbc..4944b8c 100644
--- a/src/mesa/drivers/dri/i965/intel_blit.c
+++ b/src/mesa/drivers/dri/i965/intel_blit.c
@@ -294,8 +294,8 @@ intel_miptree_blit(struct brw_context *brw,
*/
intel_miptree_slice_resolve_depth(brw, src_mt, src_level, src_slice);
intel_miptree_slice_resolve_depth(brw, dst_mt, dst_level, dst_slice);
- intel_miptree_resolve_color(brw, src_mt, 0);
- intel_miptree_resolve_color(brw, dst_mt, 0);
+ intel_miptree_resolve_color(brw, src_mt, src_level, src_slice, 1, 0);
+ intel_miptree_resolve_color(brw, dst_mt, dst_level, dst_slice, 1, 0);
if (src_flip)
src_y = minify(src_mt->physical_height0, src_level -
src_mt->first_level) - src_y - height;
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 328c770..f40dba8 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -2203,12 +2203,35 @@ intel_miptree_all_slices_resolve_depth(struct
brw_context *brw,
BLORP_HIZ_OP_DEPTH_RESOLVE);
}
+static void
+intel_miptree_check_color_resolve(const struct intel_mipmap_tree *mt,
+ unsigned level, unsigned layer)
+{
+ if (!mt->mcs_buf)
+ return;
+
+ /* Fast color clear is not supported for mipmapped surfaces. */
+ assert(level == 0 && mt->first_level == 0 && mt->last_level == 0);
+
+ /* Compression of arrayed msaa surfaces is supported. */
+ if (mt->num_samples > 1)
+ return;
+
+ /* Fast color clear is not supported for non-msaa arrays. */
+ assert(layer == 0 && mt->logical_depth0 == 1);
+
+ (void)level;
+ (void)layer;
+}
bool
intel_miptree_resolve_color(struct brw_context *brw,
- struct intel_mipmap_tree *mt,
+ struct intel_mipmap_tree *mt, unsigned level,
+ unsigned start_layer, unsigned num_layers,
int flags)
{
+ intel_miptree_check_color_resolve(mt, level, start_layer);
+
/* From gen9 onwards there is new compression scheme for single sampled
* surfaces called "lossless compressed". These don't need to be always
* resolved.
@@ -2224,10 +2247,13 @@ intel_miptree_resolve_color(struct brw_context *brw,
return false;
case INTEL_FAST_CLEAR_STATE_UNRESOLVED:
case INTEL_FAST_CLEAR_STATE_CLEAR:
+ /* For now arrayed fast clear is not supported. */
+ assert(num_layers == 1);
+
/* Fast color clear resolves only make sense for non-MSAA buffers. */
if (mt->msaa_layout == INTEL_MSAA_LAYOUT_NONE ||
intel_miptree_is_lossless_compressed(brw, mt)) {
- brw_blorp_resolve_color(brw, mt);
+ brw_blorp_resolve_color(brw, mt, level, start_layer);
return true;
} else {
return false;
@@ -2242,7 +2268,7 @@ intel_miptree_all_slices_resolve_color(struct brw_context
*brw,
struct intel_mipmap_tree *mt,
int flags)
{
- intel_miptree_resolve_color(brw, mt, flags);
+ intel_miptree_resolve_color(brw, mt, 0, 0, 1, flags);
}
/**
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
index 80cc876..be25d50 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
@@ -990,7 +990,8 @@ intel_miptree_used_for_rendering(const struct brw_context
*brw,
bool
intel_miptree_resolve_color(struct brw_context *brw,
- struct intel_mipmap_tree *mt,
+ struct intel_mipmap_tree *mt, unsigned level,
+ unsigned start_layer, unsigned num_layers,
int flags);
void
--
2.5.5
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