From: Ian Romanick <ian.d.roman...@intel.com>
It seems like maybe this should return a different type based on Gen. Q
and UQ only exist on Gen8+, but, based on the old comment, I believe
previous Gens can generate 64-bit moves.
Signed-off-by: Ian Romanick <ian.d.roman...@intel.com>
---
src/mesa/drivers/dri/i965/brw_nir.c | 6 ++----
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_nir.c
b/src/mesa/drivers/dri/i965/brw_nir.c
index 763e3ec..e9b9535 100644
--- a/src/mesa/drivers/dri/i965/brw_nir.c
+++ b/src/mesa/drivers/dri/i965/brw_nir.c
@@ -625,11 +625,9 @@ brw_type_for_nir_type(nir_alu_type type)
case nir_type_float64:
return BRW_REGISTER_TYPE_DF;
case nir_type_int64:
+ return BRW_REGISTER_TYPE_Q;
case nir_type_uint64:
- /* TODO we should only see these in moves, so for now it's ok, but when
- * we add actual 64-bit integer support we should fix this.
- */
- return BRW_REGISTER_TYPE_DF;
+ return BRW_REGISTER_TYPE_UQ;
default:
unreachable("unknown type");
}
--
2.7.4
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