Topi Pohjolainen <topi.pohjolai...@gmail.com> writes: > instead of calling unconditionally brw_emit_mi_flush() which > does: > > brw_emit_pipe_control_flush(brw, > PIPE_CONTROL_DEPTH_CACHE_FLUSH | > PIPE_CONTROL_RENDER_TARGET_FLUSH | > PIPE_CONTROL_CS_STALL); > > brw_emit_pipe_control_flush(brw, > PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE | > PIPE_CONTROL_CONST_CACHE_INVALIDATE); > > Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> > --- > src/mesa/drivers/dri/i965/brw_clear.c | 7 ++++++- > 1 file changed, 6 insertions(+), 1 deletion(-) > > diff --git a/src/mesa/drivers/dri/i965/brw_clear.c > b/src/mesa/drivers/dri/i965/brw_clear.c > index b053a7d..f6b9f96 100644 > --- a/src/mesa/drivers/dri/i965/brw_clear.c > +++ b/src/mesa/drivers/dri/i965/brw_clear.c > @@ -223,7 +223,12 @@ brw_fast_clear_depth(struct gl_context *ctx) > * by a PIPE_CONTROL command with DEPTH_STALL bit set and Then > * followed by Depth FLUSH' > */ > - brw_emit_mi_flush(brw); > + brw_emit_pipe_control_flush(brw, > + PIPE_CONTROL_DEPTH_STALL); > + > + brw_emit_pipe_control_flush(brw, > + PIPE_CONTROL_DEPTH_CACHE_FLUSH | > + PIPE_CONTROL_CS_STALL);
The CS stall is probably unnecessary (unless some other code has started making assumptions about the pipeline being completely idled at this point), but brw_emit_mi_flush(brw) already had a CS stall built-in so this shouldn't hurt much, patch is: Reviewed-by: Francisco Jerez <curroje...@riseup.net> > } > > /* Now, the HiZ buffer contains data that needs to be resolved to the > depth > -- > 2.5.5 > > _______________________________________________ > mesa-dev mailing list > mesa-dev@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/mesa-dev
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