[Mesa-dev] [PATCH 29/31] radv: handle prim id inputs to fragment shader.

[Dave Airlie]

From: Dave Airlie <airl...@redhat.com>

Signed-off-by: Dave Airlie <airl...@redhat.com>
---
 src/amd/vulkan/radv_cmd_buffer.c | 16 +++++++++++++++-
 1 file changed, 15 insertions(+), 1 deletion(-)

diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index 21c1122..92a2c96 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -701,7 +701,17 @@ radv_emit_fragment_shader(struct radv_cmd_buffer 
*cmd_buffer,
                unsigned val;
                val = S_028644_PT_SPRITE_TEX(1) | S_028644_OFFSET(0x20);
                radeon_set_context_reg(cmd_buffer->cs, 
R_028644_SPI_PS_INPUT_CNTL_0 + 4 * ps_offset, val);
-               ps_offset = 1;
+               ps_offset++;
+       }
+
+       if (ps->info.fs.prim_id_input && (vs->info.vs.prim_id_output != 
0xffffffff)) {
+               unsigned vs_offset, flat_shade;
+               unsigned val;
+               vs_offset = vs->info.vs.prim_id_output;
+               flat_shade = true;
+               val = S_028644_OFFSET(vs_offset) | 
S_028644_FLAT_SHADE(flat_shade);
+               radeon_set_context_reg(cmd_buffer->cs, 
R_028644_SPI_PS_INPUT_CNTL_0 + 4 * ps_offset, val);
+               ++ps_offset;
        }
 
        for (unsigned i = 0; i < 32 && (1u << i) <= ps->info.fs.input_mask; 
++i) {
@@ -720,6 +730,10 @@ radv_emit_fragment_shader(struct radv_cmd_buffer 
*cmd_buffer,
                }
 
                vs_offset = util_bitcount(vs->info.vs.export_mask & ((1u << i) 
- 1));
+               if (vs->info.vs.prim_id_output != 0xffffffff) {
+                       if (vs_offset >= vs->info.vs.prim_id_output)
+                               vs_offset++;
+               }
                flat_shade = !!(ps->info.fs.flat_shaded_mask & (1u << 
ps_offset));
 
                val = S_028644_OFFSET(vs_offset) | 
S_028644_FLAT_SHADE(flat_shade);
-- 
2.9.3

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