NAK, that isn't correct. Especially on APUs we can now use more than 256MB visible VRAM.
Christian. Am 30.01.2017 um 01:33 schrieb Marek Olšák:
From: Marek Olšák <marek.ol...@amd.com> the value from the kernel is wrong --- src/gallium/winsys/radeon/drm/radeon_drm_winsys.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c index 278d4f3..a8da62f 100644 --- a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c +++ b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c @@ -365,21 +365,21 @@ static bool do_winsys_init(struct radeon_drm_winsys *ws) /* Get GEM info. */ retval = drmCommandWriteRead(ws->fd, DRM_RADEON_GEM_INFO, &gem_info, sizeof(gem_info)); if (retval) { fprintf(stderr, "radeon: Failed to get MM info, error number %d\n", retval); return false; } ws->info.gart_size = gem_info.gart_size; ws->info.vram_size = gem_info.vram_size; - ws->info.vram_vis_size = gem_info.vram_visible; + ws->info.vram_vis_size = MIN2(gem_info.vram_visible, 256*1024*1024);/* Radeon allocates all buffers as contigous, which makes large allocations* unlikely to succeed. */ ws->info.max_alloc_size = MAX2(ws->info.vram_size, ws->info.gart_size) * 0.7; if (ws->info.drm_minor < 40) ws->info.max_alloc_size = MIN2(ws->info.max_alloc_size, 256*1024*1024);/* Get max clock frequency info and convert it to MHz */radeon_get_drm_value(ws->fd, RADEON_INFO_MAX_SCLK, NULL, &ws->info.max_shader_clock);
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