No f16 support as I'm not quite sure about alignment yet.
Signed-off-by: Bas Nieuwenhuizen <ba...@google.com>
---
src/amd/common/ac_nir_to_llvm.c | 17 ++++++++++++++---
1 file changed, 14 insertions(+), 3 deletions(-)
diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index 1b23a065633..657f38626e7 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -2004,7 +2004,10 @@ static void visit_store_ssbo(struct nir_to_llvm_context
*ctx,
nir_intrinsic_instr *instr)
{
const char *store_name;
+ LLVMValueRef src_data = get_src(ctx, instr->src[0]);
LLVMTypeRef data_type = ctx->f32;
+ int elem_size_mult = get_elem_bits(ctx, LLVMTypeOf(src_data)) / 32;
+ int components_32bit = elem_size_mult * instr->num_components;
unsigned writemask = nir_intrinsic_write_mask(instr);
LLVMValueRef base_data, base_offset;
LLVMValueRef params[6];
@@ -2017,10 +2020,10 @@ static void visit_store_ssbo(struct nir_to_llvm_context
*ctx,
params[4] = LLVMConstInt(ctx->i1, 0, false); /* glc */
params[5] = LLVMConstInt(ctx->i1, 0, false); /* slc */
- if (instr->num_components > 1)
- data_type = LLVMVectorType(ctx->f32, instr->num_components);
+ if (components_32bit > 1)
+ data_type = LLVMVectorType(ctx->f32, components_32bit);
- base_data = to_float(ctx, get_src(ctx, instr->src[0]));
+ base_data = to_float(ctx, src_data);
base_data = trim_vector(ctx, base_data, instr->num_components);
base_data = LLVMBuildBitCast(ctx->builder, base_data,
data_type, "");
@@ -2039,6 +2042,14 @@ static void visit_store_ssbo(struct nir_to_llvm_context
*ctx,
count = 2;
}
+ start *= elem_size_mult;
+ count *= elem_size_mult;
+
+ if (count > 4) {
+ writemask |= ((1u << (count - 4)) - 1u) << (start + 4);
+ count = 4;
+ }
+
if (count == 4) {
store_name = "llvm.amdgcn.buffer.store.v4f32";
data = base_data;
--
2.11.0
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