If a HiZ op is the first thing in the batch, we should make sure to select the render pipeline and emit state base address before proceeding.
I believe 3DSTATE_WM_HZ_OP creates 3DPRIMITIVEs internally, and dispatching those on the GPGPU pipeline seems a bit sketchy. I'm not actually sure that STATE_BASE_ADDRESS is necessary, as the depth related commands use graphics addresses, not ones relative to the base address...but we're likely to set it as part of the next operation anyway, so we should just do it right away. Cc: "17.0" <mesa-sta...@lists.freedesktop.org> Signed-off-by: Kenneth Graunke <kenn...@whitecape.org> --- src/mesa/drivers/dri/i965/gen8_depth_state.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/mesa/drivers/dri/i965/gen8_depth_state.c b/src/mesa/drivers/dri/i965/gen8_depth_state.c index a7e61354fd5..620b32df8bb 100644 --- a/src/mesa/drivers/dri/i965/gen8_depth_state.c +++ b/src/mesa/drivers/dri/i965/gen8_depth_state.c @@ -404,6 +404,9 @@ gen8_hiz_exec(struct brw_context *brw, struct intel_mipmap_tree *mt, if (op == BLORP_HIZ_OP_NONE) return; + brw_select_pipeline(brw, BRW_RENDER_PIPELINE); + brw_upload_state_base_address(brw); + /* Disable the PMA stall fix since we're about to do a HiZ operation. */ if (brw->gen == 8) gen8_write_pma_stall_bits(brw, 0); -- 2.11.0 _______________________________________________ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev