Samuel Iglesias Gonsálvez <sigles...@igalia.com> writes: > When generating the MOV INDIRECT instruction, the source type is ignored > and it is set to destination's type. However, this is going to change in a > later patch, so we need to explicitly set the proper source type. > > brw_vec8_grf() creates an float type's fs_reg by default, when the > ICP handle is actually unsigned. This patch fixes these cases before > applying the aforementioned patch. > > Signed-off-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> > Cc: "17.0" <mesa-sta...@lists.freedesktop.org> > --- > src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions(-) > > diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp > b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp > index 4aaf84964e9..2db44d5ba2b 100644 > --- a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp > +++ b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp > @@ -2093,7 +2093,7 @@ fs_visitor::emit_gs_input_load(const fs_reg &dst, > * we might read up to nir->info->gs.vertices_in registers. > */ > bld.emit(SHADER_OPCODE_MOV_INDIRECT, icp_handle, > - fs_reg(brw_vec8_grf(first_icp_handle, 0)), > + retype(fs_reg(brw_vec8_grf(first_icp_handle, 0)), > icp_handle.type),
I believe you can drop the explicit fs_reg constructor call here and below. > fs_reg(icp_offset_bytes), > brw_imm_ud(nir->info->gs.vertices_in * REG_SIZE)); > } > @@ -2124,7 +2124,7 @@ fs_visitor::emit_gs_input_load(const fs_reg &dst, > * we might read up to ceil(nir->info->gs.vertices_in / 8) > registers. > */ > bld.emit(SHADER_OPCODE_MOV_INDIRECT, icp_handle, > - fs_reg(brw_vec8_grf(first_icp_handle, 0)), > + retype(fs_reg(brw_vec8_grf(first_icp_handle, 0)), > BRW_REGISTER_TYPE_UD), You could specify the type as icp_handle.type for consistency here. With that fixed: Reviewed-by: Francisco Jerez <curroje...@riseup.net> > fs_reg(icp_offset_bytes), > brw_imm_ud(DIV_ROUND_UP(nir->info->gs.vertices_in, 8) * > REG_SIZE)); > @@ -2464,7 +2464,7 @@ fs_visitor::nir_emit_tcs_intrinsic(const fs_builder > &bld, > > /* Start at g1. We might read up to 4 registers. */ > bld.emit(SHADER_OPCODE_MOV_INDIRECT, icp_handle, > - fs_reg(brw_vec8_grf(1, 0)), vertex_offset_bytes, > + retype(fs_reg(brw_vec8_grf(1, 0)), icp_handle.type), > vertex_offset_bytes, > brw_imm_ud(4 * REG_SIZE)); > } > > -- > 2.11.0
signature.asc
Description: PGP signature
_______________________________________________ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
