From: Marek Olšák <marek.ol...@amd.com>
They are too old.
---
configure.ac | 4 +--
src/amd/common/ac_llvm_build.c | 30 ++++++++--------------
src/amd/common/ac_llvm_helper.cpp | 6 ++---
src/amd/common/ac_llvm_util.c | 16 +-----------
src/gallium/drivers/radeon/r600_pipe_common.c | 8 +++---
src/gallium/drivers/radeonsi/si_pipe.c | 13 ++--------
src/gallium/drivers/radeonsi/si_shader.c | 2 +-
src/gallium/drivers/radeonsi/si_shader_tgsi_alu.c | 6 ++---
.../drivers/radeonsi/si_shader_tgsi_setup.c | 8 ------
src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c | 8 ------
10 files changed, 25 insertions(+), 76 deletions(-)
diff --git a/configure.ac b/configure.ac
index 73bd749..21a73b0 100644
--- a/configure.ac
+++ b/configure.ac
@@ -97,22 +97,22 @@ XCBGLX_REQUIRED=1.8.1
XDAMAGE_REQUIRED=1.1
XSHMFENCE_REQUIRED=1.1
XVMC_REQUIRED=1.0.6
PYTHON_MAKO_REQUIRED=0.8.0
LIBSENSORS_REQUIRED=4.0.0
ZLIB_REQUIRED=1.2.8
dnl LLVM versions
LLVM_REQUIRED_GALLIUM=3.3.0
LLVM_REQUIRED_OPENCL=3.6.0
-LLVM_REQUIRED_R600=3.6.0
-LLVM_REQUIRED_RADEONSI=3.6.0
+LLVM_REQUIRED_R600=3.8.0
+LLVM_REQUIRED_RADEONSI=3.8.0
LLVM_REQUIRED_RADV=3.9.0
LLVM_REQUIRED_SWR=3.9.0
dnl Check for progs
AC_PROG_CPP
AC_PROG_CC
AC_PROG_CXX
AM_PROG_CC_C_O
AM_PROG_AS
AX_CHECK_GNU_MAKE
diff --git a/src/amd/common/ac_llvm_build.c b/src/amd/common/ac_llvm_build.c
index 0039e63..8996159 100644
--- a/src/amd/common/ac_llvm_build.c
+++ b/src/amd/common/ac_llvm_build.c
@@ -785,36 +785,30 @@ static void set_range_metadata(struct ac_llvm_context
*ctx,
md_args[1] = LLVMConstInt(type, hi, false);
range_md = LLVMMDNodeInContext(context, md_args, 2);
LLVMSetMetadata(value, ctx->range_md_kind, range_md);
}
LLVMValueRef
ac_get_thread_id(struct ac_llvm_context *ctx)
{
LLVMValueRef tid;
- if (HAVE_LLVM < 0x0308) {
- tid = ac_build_intrinsic(ctx, "llvm.SI.tid",
- ctx->i32,
- NULL, 0, AC_FUNC_ATTR_READNONE);
- } else {
- LLVMValueRef tid_args[2];
- tid_args[0] = LLVMConstInt(ctx->i32, 0xffffffff, false);
- tid_args[1] = LLVMConstInt(ctx->i32, 0, false);
- tid_args[1] = ac_build_intrinsic(ctx,
- "llvm.amdgcn.mbcnt.lo",
ctx->i32,
- tid_args, 2,
AC_FUNC_ATTR_READNONE);
-
- tid = ac_build_intrinsic(ctx, "llvm.amdgcn.mbcnt.hi",
- ctx->i32, tid_args,
- 2, AC_FUNC_ATTR_READNONE);
- }
+ LLVMValueRef tid_args[2];
+ tid_args[0] = LLVMConstInt(ctx->i32, 0xffffffff, false);
+ tid_args[1] = LLVMConstInt(ctx->i32, 0, false);
+ tid_args[1] = ac_build_intrinsic(ctx,
+ "llvm.amdgcn.mbcnt.lo", ctx->i32,
+ tid_args, 2, AC_FUNC_ATTR_READNONE);
+
+ tid = ac_build_intrinsic(ctx, "llvm.amdgcn.mbcnt.hi",
+ ctx->i32, tid_args,
+ 2, AC_FUNC_ATTR_READNONE);
set_range_metadata(ctx, tid, 0, 64);
return tid;
}
/*
* SI implements derivatives using the local data store (LDS)
* All writes to the LDS happen in all executing threads at
* the same time. TID is the Thread ID for the current
* thread and is a value between 0 and 63, representing
* the thread's position in the wavefront.
@@ -965,29 +959,27 @@ LLVMValueRef ac_build_clamp(struct ac_llvm_context *ctx,
LLVMValueRef value)
};
min[1] = ac_build_intrinsic(ctx, "llvm.maxnum.f32",
ctx->f32, max, 2,
AC_FUNC_ATTR_READNONE);
return ac_build_intrinsic(ctx, "llvm.minnum.f32",
ctx->f32, min, 2,
AC_FUNC_ATTR_READNONE);
}
- const char *intr = HAVE_LLVM >= 0x0308 ? "llvm.AMDGPU.clamp." :
- "llvm.AMDIL.clamp.";
LLVMValueRef args[3] = {
value,
LLVMConstReal(ctx->f32, 0),
LLVMConstReal(ctx->f32, 1),
};
- return ac_build_intrinsic(ctx, intr, ctx->f32, args, 3,
+ return ac_build_intrinsic(ctx, "llvm.AMDGPU.clamp.", ctx->f32, args, 3,
AC_FUNC_ATTR_READNONE |
AC_FUNC_ATTR_LEGACY);
}
void ac_build_export(struct ac_llvm_context *ctx, struct ac_export_args *a)
{
LLVMValueRef args[9];
if (HAVE_LLVM >= 0x0500) {
args[0] = LLVMConstInt(ctx->i32, a->target, 0);
diff --git a/src/amd/common/ac_llvm_helper.cpp
b/src/amd/common/ac_llvm_helper.cpp
index 594339e..4f03103 100644
--- a/src/amd/common/ac_llvm_helper.cpp
+++ b/src/amd/common/ac_llvm_helper.cpp
@@ -19,24 +19,22 @@
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial portions
* of the Software.
*
*/
/* based on Marek's patch to lp_bld_misc.cpp */
// Workaround http://llvm.org/PR23628
-#if HAVE_LLVM >= 0x0307
-# pragma push_macro("DEBUG")
-# undef DEBUG
-#endif
+#pragma push_macro("DEBUG")
+#undef DEBUG
#include "ac_llvm_util.h"
#include <llvm-c/Core.h>
#include <llvm/Target/TargetOptions.h>
#include <llvm/ExecutionEngine/ExecutionEngine.h>
#include <llvm/IR/Attributes.h>
void ac_add_attr_dereferenceable(LLVMValueRef val, uint64_t bytes)
{
llvm::Argument *A = llvm::unwrap<llvm::Argument>(val);
diff --git a/src/amd/common/ac_llvm_util.c b/src/amd/common/ac_llvm_util.c
index 4b5d2fe..a2fe631 100644
--- a/src/amd/common/ac_llvm_util.c
+++ b/src/amd/common/ac_llvm_util.c
@@ -28,31 +28,24 @@
#include <llvm-c/Core.h>
#include "c11/threads.h"
#include <assert.h>
#include <stdio.h>
#include <string.h>
static void ac_init_llvm_target()
{
-#if HAVE_LLVM < 0x0307
- LLVMInitializeR600TargetInfo();
- LLVMInitializeR600Target();
- LLVMInitializeR600TargetMC();
- LLVMInitializeR600AsmPrinter();
-#else
LLVMInitializeAMDGPUTargetInfo();
LLVMInitializeAMDGPUTarget();
LLVMInitializeAMDGPUTargetMC();
LLVMInitializeAMDGPUAsmPrinter();
-#endif
}
static once_flag ac_init_llvm_target_once_flag = ONCE_FLAG_INIT;
static LLVMTargetRef ac_get_llvm_target(const char *triple)
{
LLVMTargetRef target = NULL;
char *err_message = NULL;
call_once(&ac_init_llvm_target_once_flag, ac_init_llvm_target);
@@ -90,32 +83,25 @@ static const char *ac_get_llvm_processor_name(enum
radeon_family family)
case CHIP_HAWAII:
return "hawaii";
case CHIP_MULLINS:
return "mullins";
case CHIP_TONGA:
return "tonga";
case CHIP_ICELAND:
return "iceland";
case CHIP_CARRIZO:
return "carrizo";
-#if HAVE_LLVM <= 0x0307
- case CHIP_FIJI:
- return "tonga";
- case CHIP_STONEY:
- return "carrizo";
-#else
case CHIP_FIJI:
return "fiji";
case CHIP_STONEY:
return "stoney";
-#endif
-#if HAVE_LLVM <= 0x0308
+#if HAVE_LLVM == 0x0308
case CHIP_POLARIS10:
return "tonga";
case CHIP_POLARIS11:
return "tonga";
#else
case CHIP_POLARIS10:
return "polaris10";
case CHIP_POLARIS11:
return "polaris11";
#endif
diff --git a/src/gallium/drivers/radeon/r600_pipe_common.c
b/src/gallium/drivers/radeon/r600_pipe_common.c
index 5a6f960..26d0775 100644
--- a/src/gallium/drivers/radeon/r600_pipe_common.c
+++ b/src/gallium/drivers/radeon/r600_pipe_common.c
@@ -36,21 +36,21 @@
#include "vl/vl_decoder.h"
#include "vl/vl_video_buffer.h"
#include "radeon/radeon_video.h"
#include <inttypes.h>
#include <sys/utsname.h>
#ifndef HAVE_LLVM
#define HAVE_LLVM 0
#endif
-#if HAVE_LLVM >= 0x0306
+#if HAVE_LLVM
#include <llvm-c/TargetMachine.h>
#endif
#ifndef MESA_LLVM_VERSION_PATCH
#define MESA_LLVM_VERSION_PATCH 0
#endif
struct r600_multi_fence {
struct pipe_reference reference;
struct pipe_fence_handle *gfx;
@@ -786,21 +786,21 @@ static const char* r600_get_chip_name(struct
r600_common_screen *rscreen)
static void r600_disk_cache_create(struct r600_common_screen *rscreen)
{
uint32_t mesa_timestamp;
if (disk_cache_get_function_timestamp(r600_disk_cache_create,
&mesa_timestamp)) {
char *timestamp_str;
int res = -1;
if (rscreen->chip_class < SI) {
res = asprintf(×tamp_str, "%u",mesa_timestamp);
}
-#if HAVE_LLVM >= 0x0306
+#if HAVE_LLVM
else {
uint32_t llvm_timestamp;
if
(disk_cache_get_function_timestamp(LLVMInitializeAMDGPUTargetInfo,
&llvm_timestamp))
{
res = asprintf(×tamp_str, "%u_%u",
mesa_timestamp, llvm_timestamp);
}
}
#endif
if (res != -1) {
@@ -931,23 +931,23 @@ const char *r600_get_llvm_processor_name(enum
radeon_family family)
case CHIP_BONAIRE: return "bonaire";
case CHIP_KABINI: return "kabini";
case CHIP_KAVERI: return "kaveri";
case CHIP_HAWAII: return "hawaii";
case CHIP_MULLINS:
return "mullins";
case CHIP_TONGA: return "tonga";
case CHIP_ICELAND: return "iceland";
case CHIP_CARRIZO: return "carrizo";
case CHIP_FIJI:
- return HAVE_LLVM >= 0x0308 ? "fiji" : "carrizo";
+ return "fiji";
case CHIP_STONEY:
- return HAVE_LLVM >= 0x0308 ? "stoney" : "carrizo";
+ return "stoney";
case CHIP_POLARIS10:
return HAVE_LLVM >= 0x0309 ? "polaris10" : "carrizo";
case CHIP_POLARIS11:
case CHIP_POLARIS12: /* same as polaris11 */
return HAVE_LLVM >= 0x0309 ? "polaris11" : "carrizo";
default:
return "";
}
}
diff --git a/src/gallium/drivers/radeonsi/si_pipe.c
b/src/gallium/drivers/radeonsi/si_pipe.c
index a0e90a8..d04abb6 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.c
+++ b/src/gallium/drivers/radeonsi/si_pipe.c
@@ -121,24 +121,22 @@ static void si_emit_string_marker(struct pipe_context
*ctx,
dd_parse_apitrace_marker(string, len, &sctx->apitrace_call_number);
}
static LLVMTargetMachineRef
si_create_llvm_target_machine(struct si_screen *sscreen)
{
const char *triple = "amdgcn--";
return LLVMCreateTargetMachine(si_llvm_get_amdgpu_target(triple),
triple,
r600_get_llvm_processor_name(sscreen->b.family),
-#if HAVE_LLVM >= 0x0308
sscreen->b.debug_flags & DBG_SI_SCHED ?
SI_LLVM_DEFAULT_FEATURES
",+si-scheduler" :
-#endif
SI_LLVM_DEFAULT_FEATURES,
LLVMCodeGenLevelDefault,
LLVMRelocDefault,
LLVMCodeModelDefault);
}
static struct pipe_context *si_create_context(struct pipe_screen *screen,
void *priv, unsigned flags)
{
struct si_context *sctx = CALLOC_STRUCT(si_context);
@@ -410,24 +408,23 @@ static int si_get_param(struct pipe_screen* pscreen, enum
pipe_cap param)
case PIPE_CAP_GENERATE_MIPMAP:
case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
case PIPE_CAP_STRING_MARKER:
case PIPE_CAP_CLEAR_TEXTURE:
case PIPE_CAP_CULL_DISTANCE:
case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
+ case PIPE_CAP_DOUBLES:
return 1;
- case PIPE_CAP_DOUBLES:
- return HAVE_LLVM >= 0x0307;
case PIPE_CAP_INT64:
case PIPE_CAP_INT64_DIVMOD:
return HAVE_LLVM >= 0x0309;
case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
return !SI_BIG_ENDIAN && sscreen->b.info.has_userptr;
case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
return (sscreen->b.info.drm_major == 2 &&
sscreen->b.info.drm_minor >= 43) ||
@@ -449,22 +446,21 @@ static int si_get_param(struct pipe_screen* pscreen, enum
pipe_cap param)
case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
case PIPE_CAP_MAX_VERTEX_STREAMS:
return 4;
case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
return HAVE_LLVM >= 0x0309 ? 4 : 0;
case PIPE_CAP_GLSL_FEATURE_LEVEL:
if (si_have_tgsi_compute(sscreen))
return 450;
- return HAVE_LLVM >= 0x0309 ? 420 :
- HAVE_LLVM >= 0x0307 ? 410 : 330;
+ return HAVE_LLVM >= 0x0309 ? 420 : 410;
case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
return MIN2(sscreen->b.info.max_alloc_size, INT_MAX);
case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
/* SI doesn't support unaligned loads.
* CIK needs DRM 2.50.0 on radeon. */
return sscreen->b.chip_class == SI ||
@@ -570,26 +566,22 @@ static int si_get_param(struct pipe_screen* pscreen, enum
pipe_cap param)
static int si_get_shader_param(struct pipe_screen* pscreen, unsigned shader,
enum pipe_shader_cap param)
{
struct si_screen *sscreen = (struct si_screen *)pscreen;
switch(shader)
{
case PIPE_SHADER_FRAGMENT:
case PIPE_SHADER_VERTEX:
case PIPE_SHADER_GEOMETRY:
- break;
case PIPE_SHADER_TESS_CTRL:
case PIPE_SHADER_TESS_EVAL:
- /* LLVM 3.6.2 is required for tessellation because of bug fixes
there */
- if (HAVE_LLVM == 0x0306 && MESA_LLVM_VERSION_PATCH < 2)
- return 0;
break;
case PIPE_SHADER_COMPUTE:
switch (param) {
case PIPE_SHADER_CAP_PREFERRED_IR:
return PIPE_SHADER_IR_NATIVE;
case PIPE_SHADER_CAP_SUPPORTED_IRS: {
int ir = 1 << PIPE_SHADER_IR_NATIVE;
if (si_have_tgsi_compute(sscreen))
@@ -829,21 +821,20 @@ struct pipe_screen *radeonsi_screen_create(struct
radeon_winsys *ws)
sscreen->b.info.pfp_fw_version >= 121 &&
sscreen->b.info.me_fw_version >= 87);
sscreen->has_ds_bpermute = HAVE_LLVM >= 0x0309 &&
sscreen->b.chip_class >= VI;
sscreen->b.has_cp_dma = true;
sscreen->b.has_streamout = true;
pipe_mutex_init(sscreen->shader_parts_mutex);
sscreen->use_monolithic_shaders =
- HAVE_LLVM < 0x0308 ||
(sscreen->b.debug_flags & DBG_MONOLITHIC_SHADERS) != 0;
sscreen->b.barrier_flags.cp_to_L2 = SI_CONTEXT_INV_SMEM_L1 |
SI_CONTEXT_INV_VMEM_L1 |
SI_CONTEXT_INV_GLOBAL_L2;
sscreen->b.barrier_flags.compute_to_L2 = SI_CONTEXT_CS_PARTIAL_FLUSH;
if (debug_get_bool_option("RADEON_DUMP_SHADERS", false))
sscreen->b.debug_flags |= DBG_FS | DBG_VS | DBG_GS | DBG_PS |
DBG_CS;
diff --git a/src/gallium/drivers/radeonsi/si_shader.c
b/src/gallium/drivers/radeonsi/si_shader.c
index edfa284..ba29661 100644
--- a/src/gallium/drivers/radeonsi/si_shader.c
+++ b/src/gallium/drivers/radeonsi/si_shader.c
@@ -593,21 +593,21 @@ static LLVMValueRef get_indirect_index(struct
si_shader_context *ctx,
static LLVMValueRef get_bounded_indirect_index(struct si_shader_context *ctx,
const struct tgsi_ind_register
*ind,
int rel_index, unsigned num)
{
LLVMValueRef result = get_indirect_index(ctx, ind, rel_index);
/* LLVM 3.8: If indirect resource indexing is used:
* - SI & CIK hang
* - VI crashes
*/
- if (HAVE_LLVM <= 0x0308)
+ if (HAVE_LLVM == 0x0308)
return LLVMGetUndef(ctx->i32);
return si_llvm_bound_index(ctx, result, num);
}
/**
* Calculate a dword address given an input or output register and a stride.
*/
static LLVMValueRef get_dw_address(struct si_shader_context *ctx,
diff --git a/src/gallium/drivers/radeonsi/si_shader_tgsi_alu.c
b/src/gallium/drivers/radeonsi/si_shader_tgsi_alu.c
index eeff71d..1e9a604 100644
--- a/src/gallium/drivers/radeonsi/si_shader_tgsi_alu.c
+++ b/src/gallium/drivers/radeonsi/si_shader_tgsi_alu.c
@@ -723,22 +723,21 @@ static void emit_rsq(const struct lp_build_tgsi_action
*action,
}
void si_shader_context_init_alu(struct lp_build_tgsi_context *bld_base)
{
lp_set_default_actions(bld_base);
bld_base->op_actions[TGSI_OPCODE_AND].emit = emit_and;
bld_base->op_actions[TGSI_OPCODE_ARL].emit = emit_arl;
bld_base->op_actions[TGSI_OPCODE_BFI].emit = emit_bfi;
bld_base->op_actions[TGSI_OPCODE_BREV].emit =
build_tgsi_intrinsic_nomem;
- bld_base->op_actions[TGSI_OPCODE_BREV].intr_name =
- HAVE_LLVM >= 0x0308 ? "llvm.bitreverse.i32" :
"llvm.AMDGPU.brev";
+ bld_base->op_actions[TGSI_OPCODE_BREV].intr_name =
"llvm.bitreverse.i32";
bld_base->op_actions[TGSI_OPCODE_CEIL].emit =
build_tgsi_intrinsic_nomem;
bld_base->op_actions[TGSI_OPCODE_CEIL].intr_name = "llvm.ceil.f32";
bld_base->op_actions[TGSI_OPCODE_CMP].emit = emit_cmp;
bld_base->op_actions[TGSI_OPCODE_COS].emit = build_tgsi_intrinsic_nomem;
bld_base->op_actions[TGSI_OPCODE_COS].intr_name = "llvm.cos.f32";
bld_base->op_actions[TGSI_OPCODE_DABS].emit =
build_tgsi_intrinsic_nomem;
bld_base->op_actions[TGSI_OPCODE_DABS].intr_name = "llvm.fabs.f64";
bld_base->op_actions[TGSI_OPCODE_DFMA].emit =
build_tgsi_intrinsic_nomem;
bld_base->op_actions[TGSI_OPCODE_DFMA].intr_name = "llvm.fma.f64";
bld_base->op_actions[TGSI_OPCODE_DFRAC].emit = emit_frac;
@@ -747,22 +746,21 @@ void si_shader_context_init_alu(struct
lp_build_tgsi_context *bld_base)
bld_base->op_actions[TGSI_OPCODE_DSEQ].emit = emit_dcmp;
bld_base->op_actions[TGSI_OPCODE_DSGE].emit = emit_dcmp;
bld_base->op_actions[TGSI_OPCODE_DSLT].emit = emit_dcmp;
bld_base->op_actions[TGSI_OPCODE_DSNE].emit = emit_dcmp;
bld_base->op_actions[TGSI_OPCODE_DRSQ].emit =
build_tgsi_intrinsic_nomem;
bld_base->op_actions[TGSI_OPCODE_DRSQ].intr_name =
HAVE_LLVM >= 0x0309 ? "llvm.amdgcn.rsq.f64" :
"llvm.AMDGPU.rsq.f64";
bld_base->op_actions[TGSI_OPCODE_DSQRT].emit =
build_tgsi_intrinsic_nomem;
bld_base->op_actions[TGSI_OPCODE_DSQRT].intr_name = "llvm.sqrt.f64";
bld_base->op_actions[TGSI_OPCODE_EX2].emit = build_tgsi_intrinsic_nomem;
- bld_base->op_actions[TGSI_OPCODE_EX2].intr_name =
- HAVE_LLVM >= 0x0308 ? "llvm.exp2.f32" : "llvm.AMDIL.exp.";
+ bld_base->op_actions[TGSI_OPCODE_EX2].intr_name = "llvm.exp2.f32";
bld_base->op_actions[TGSI_OPCODE_FLR].emit = build_tgsi_intrinsic_nomem;
bld_base->op_actions[TGSI_OPCODE_FLR].intr_name = "llvm.floor.f32";
bld_base->op_actions[TGSI_OPCODE_FMA].emit =
bld_base->op_actions[TGSI_OPCODE_MAD].emit;
bld_base->op_actions[TGSI_OPCODE_FRC].emit = emit_frac;
bld_base->op_actions[TGSI_OPCODE_F2I].emit = emit_f2i;
bld_base->op_actions[TGSI_OPCODE_F2U].emit = emit_f2u;
bld_base->op_actions[TGSI_OPCODE_FSEQ].emit = emit_fcmp;
bld_base->op_actions[TGSI_OPCODE_FSGE].emit = emit_fcmp;
bld_base->op_actions[TGSI_OPCODE_FSLT].emit = emit_fcmp;
diff --git a/src/gallium/drivers/radeonsi/si_shader_tgsi_setup.c
b/src/gallium/drivers/radeonsi/si_shader_tgsi_setup.c
index c7cf632..5c63b73 100644
--- a/src/gallium/drivers/radeonsi/si_shader_tgsi_setup.c
+++ b/src/gallium/drivers/radeonsi/si_shader_tgsi_setup.c
@@ -113,32 +113,24 @@ void si_llvm_shader_type(LLVMValueRef F, unsigned type)
if (HAVE_LLVM >= 0x309)
LLVMSetFunctionCallConv(F, calling_conv);
else
si_llvm_add_attribute(F, "ShaderType", llvm_type);
}
static void init_amdgpu_target()
{
gallivm_init_llvm_targets();
-#if HAVE_LLVM < 0x0307
- LLVMInitializeR600TargetInfo();
- LLVMInitializeR600Target();
- LLVMInitializeR600TargetMC();
- LLVMInitializeR600AsmPrinter();
-#else
LLVMInitializeAMDGPUTargetInfo();
LLVMInitializeAMDGPUTarget();
LLVMInitializeAMDGPUTargetMC();
LLVMInitializeAMDGPUAsmPrinter();
-
-#endif
}
static once_flag init_amdgpu_target_once_flag = ONCE_FLAG_INIT;
LLVMTargetRef si_llvm_get_amdgpu_target(const char *triple)
{
LLVMTargetRef target = NULL;
char *err_message = NULL;
call_once(&init_amdgpu_target_once_flag, init_amdgpu_target);
diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c
b/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c
index da9371d..4a4e06c 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c
@@ -223,28 +223,20 @@ static bool do_winsys_init(struct amdgpu_winsys *ws, int
fd)
ws->info.chip_class = VI;
else if (ws->info.family >= CHIP_BONAIRE)
ws->info.chip_class = CIK;
else if (ws->info.family >= CHIP_TAHITI)
ws->info.chip_class = SI;
else {
fprintf(stderr, "amdgpu: Unknown family.\n");
goto fail;
}
- /* LLVM 3.6.1 is required for VI. */
- if (ws->info.chip_class >= VI &&
- HAVE_LLVM == 0x0306 && MESA_LLVM_VERSION_PATCH < 1) {
- fprintf(stderr, "amdgpu: LLVM 3.6.1 is required, got LLVM %i.%i.%i\n",
- HAVE_LLVM >> 8, HAVE_LLVM & 255, MESA_LLVM_VERSION_PATCH);
- goto fail;
- }
-
/* family and rev_id are for addrlib */
switch (ws->info.family) {
case CHIP_TAHITI:
ws->family = FAMILY_SI;
ws->rev_id = SI_TAHITI_P_A0;
break;
case CHIP_PITCAIRN:
ws->family = FAMILY_SI;
ws->rev_id = SI_PITCAIRN_PM_A0;
break;
--
2.7.4
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