The function convert_IF_ELSE_to_ADD() assumes that it doesn't have to
modify the destination and src0 fields of the instruction that it's
modifying, since prior to Gen6, IF and ELSE instructions use the IP
register in these fields.
In Gen6 and later, this is no longer true. Currently this isn't a
problem, since converting IF and ELSE to ADD doesn't work on Gen6 (see
previous commit), and since we don't use SPF mode on Gen7 yet. But we
probably will use SPF mode on Gen7 eventually (for geometry shaders)
so it seems worth fixing the bug now.
---
src/mesa/drivers/dri/i965/brw_eu_emit.c | 10 +++++++---
1 files changed, 7 insertions(+), 3 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c
b/src/mesa/drivers/dri/i965/brw_eu_emit.c
index a1cd00e..4ef376a 100644
--- a/src/mesa/drivers/dri/i965/brw_eu_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c
@@ -1022,17 +1022,21 @@ convert_IF_ELSE_to_ADD(struct brw_compile *p,
*/
if_inst->header.opcode = BRW_OPCODE_ADD;
if_inst->header.predicate_inverse = 1;
+ brw_set_dest(p, if_inst, brw_ip_reg());
+ brw_set_src0(p, if_inst, brw_ip_reg());
if (else_inst != NULL) {
/* Convert ELSE to an ADD instruction that points where the ENDIF
* would be.
*/
else_inst->header.opcode = BRW_OPCODE_ADD;
+ brw_set_dest(p, else_inst, brw_ip_reg());
+ brw_set_src0(p, else_inst, brw_ip_reg());
- if_inst->bits3.ud = (else_inst - if_inst + 1) * 16;
- else_inst->bits3.ud = (next_inst - else_inst) * 16;
+ brw_set_src1(p, if_inst, brw_imm_d((else_inst - if_inst + 1) * 16));
+ brw_set_src1(p, else_inst, brw_imm_d((next_inst - else_inst) * 16));
} else {
- if_inst->bits3.ud = (next_inst - if_inst) * 16;
+ brw_set_src1(p, if_inst, brw_imm_d((next_inst - if_inst) * 16));
}
}
--
1.7.6.4
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