Reviewed-by: Jason Ekstrand <ja...@jlekstrand.net> Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> --- src/mesa/drivers/dri/i965/brw_blorp.c | 8 ++++---- src/mesa/drivers/dri/i965/brw_tex_layout.c | 19 +------------------ src/mesa/drivers/dri/i965/gen6_depth_state.c | 4 ++-- src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 5 +---- 4 files changed, 8 insertions(+), 28 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c b/src/mesa/drivers/dri/i965/brw_blorp.c index 5a9d21c..fda3e6f 100644 --- a/src/mesa/drivers/dri/i965/brw_blorp.c +++ b/src/mesa/drivers/dri/i965/brw_blorp.c @@ -162,10 +162,9 @@ blorp_surf_for_miptree(struct brw_context *brw, * it any further. See blorp_emit_depth_stencil_config(). */ surf->addr.offset += brw_stencil_all_slices_at_each_lod_offset( - surf->surf, mt, *level); + surf->surf, *level); - assert(brw_stencil_all_slices_at_each_lod_offset( - surf->surf, mt, *level) == + assert(brw_stencil_all_slices_at_each_lod_offset(surf->surf, *level) == mt->level[*level].level_y * mt->pitch + mt->level[*level].level_x * 64); @@ -248,7 +247,8 @@ blorp_surf_for_miptree(struct brw_context *brw, */ surf->aux_addr.offset = brw_hiz_all_slices_at_each_lod_offset( &surf->surf->phys_level0_sa, surf->surf->dim, - surf->surf->levels, surf->surf->format, hiz_mt, *level); + surf->surf->levels, surf->surf->format, *level); + assert(surf->aux_addr.offset == intel_miptree_get_aligned_offset( hiz_mt, diff --git a/src/mesa/drivers/dri/i965/brw_tex_layout.c b/src/mesa/drivers/dri/i965/brw_tex_layout.c index e8eedd7..76d6ba0 100644 --- a/src/mesa/drivers/dri/i965/brw_tex_layout.c +++ b/src/mesa/drivers/dri/i965/brw_tex_layout.c @@ -198,11 +198,8 @@ all_slices_at_each_lod_y_offset(const struct isl_extent4d *phys_level0_sa, uint32_t brw_stencil_all_slices_at_each_lod_offset(const struct isl_surf *surf, - const struct intel_mipmap_tree *mt, unsigned level) { - assert(mt->array_layout == ALL_SLICES_AT_EACH_LOD); - const unsigned halign = 64; const unsigned valign = 64; const unsigned level_x = all_slices_at_each_lod_x_offset( @@ -210,9 +207,6 @@ brw_stencil_all_slices_at_each_lod_offset(const struct isl_surf *surf, const unsigned level_y = all_slices_at_each_lod_y_offset( &surf->phys_level0_sa, surf->dim, valign, level); - assert(level_x == mt->level[level].level_x); - assert(level_y == mt->level[level].level_y); - /* From Vol 2a, 11.5.6.2.1 3DSTATE_STENCIL_BUFFER, field "Surface Pitch": * The pitch must be set to 2x the value computed based on width, as * the stencil buffer is stored with two rows interleaved. @@ -223,8 +217,6 @@ brw_stencil_all_slices_at_each_lod_offset(const struct isl_surf *surf, */ const unsigned two_rows_interleaved_pitch = surf->row_pitch / 2; - assert(two_rows_interleaved_pitch == mt->pitch); - return level_y * two_rows_interleaved_pitch + level_x * 64; } @@ -248,12 +240,8 @@ uint32_t brw_hiz_all_slices_at_each_lod_offset( const struct isl_extent4d *phys_level0_sa, enum isl_surf_dim dim, unsigned num_levels, - enum isl_format format, - const struct intel_mipmap_tree *mt, - unsigned level) + enum isl_format format, unsigned level) { - assert(mt->array_layout == ALL_SLICES_AT_EACH_LOD); - const uint32_t cpp = isl_format_get_layout(format)->bpb / 8; const uint32_t halign = 128 / cpp; const uint32_t valign = 32; @@ -264,11 +252,6 @@ brw_hiz_all_slices_at_each_lod_offset( const uint32_t pitch = brw_get_mipmap_total_width( phys_level0_sa->width, num_levels, halign) * cpp; - assert(level_x == mt->level[level].level_x); - assert(level_y == mt->level[level].level_y); - assert(pitch == mt->pitch); - assert(cpp == mt->cpp); - return level_y * pitch + level_x / halign * 4096; } diff --git a/src/mesa/drivers/dri/i965/gen6_depth_state.c b/src/mesa/drivers/dri/i965/gen6_depth_state.c index e84ecac..f709ee7 100644 --- a/src/mesa/drivers/dri/i965/gen6_depth_state.c +++ b/src/mesa/drivers/dri/i965/gen6_depth_state.c @@ -173,7 +173,7 @@ gen6_emit_depth_stencil_hiz(struct brw_context *brw, */ const uint32_t offset = brw_hiz_all_slices_at_each_lod_offset( &temp_surf.phys_level0_sa, temp_surf.dim, temp_surf.levels, - temp_surf.format, hiz_mt, lod); + temp_surf.format, lod); assert(offset == intel_miptree_get_aligned_offset( hiz_mt, @@ -206,7 +206,7 @@ gen6_emit_depth_stencil_hiz(struct brw_context *brw, intel_miptree_get_isl_surf(brw, stencil_mt, &temp_surf); offset = brw_stencil_all_slices_at_each_lod_offset( - &temp_surf, stencil_mt, lod); + &temp_surf, lod); assert(offset == stencil_mt->level[lod].level_y * stencil_mt->pitch + stencil_mt->level[lod].level_x * 64); diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h index 6dea82b..5707037 100644 --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h @@ -978,16 +978,13 @@ brw_get_mipmap_total_width(unsigned w0, unsigned num_levels, unsigned halign); uint32_t brw_stencil_all_slices_at_each_lod_offset(const struct isl_surf *surf, - const struct intel_mipmap_tree *mt, uint32_t level); uint32_t brw_hiz_all_slices_at_each_lod_offset( const struct isl_extent4d *phys_level0_sa, enum isl_surf_dim dim, unsigned num_levels, - enum isl_format format, - const struct intel_mipmap_tree *mt, - unsigned level); + enum isl_format format, unsigned level); bool brw_miptree_layout(struct brw_context *brw, -- 2.9.3 _______________________________________________ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev