On 02.06.2017 15:01, Marek Olšák wrote:
On Wed, May 3, 2017 at 3:58 PM, Nicolai Hähnle <nhaeh...@gmail.com> wrote:
From: Nicolai Hähnle <nicolai.haeh...@amd.com>
Cc: mesa-sta...@lists.freedesktop.org
---
src/gallium/drivers/radeonsi/si_state_draw.c | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c
b/src/gallium/drivers/radeonsi/si_state_draw.c
index e6a9ee0..3d1d1f8 100644
--- a/src/gallium/drivers/radeonsi/si_state_draw.c
+++ b/src/gallium/drivers/radeonsi/si_state_draw.c
@@ -181,20 +181,34 @@ static void si_emit_derived_tess_state(struct si_context
*sctx,
/* Not necessary for correctness, but improves performance. The
* specific value is taken from the proprietary driver.
*/
*num_patches = MIN2(*num_patches, 40);
/* SI bug workaround - limit LS-HS threadgroups to only one wave. */
if (sctx->b.chip_class == SI) {
unsigned one_wave = 64 / MAX2(num_tcs_input_cp,
num_tcs_output_cp);
*num_patches = MIN2(*num_patches, one_wave);
+
+ if (sctx->screen->b.info.max_se == 1) {
+ /* The VGT HS block increments the patch ID
unconditionally
+ * within a single threadgroup. This results in
incorrect
+ * patch IDs when instanced draws are used.
+ *
+ * The intended solution is to restrict threadgroups to
+ * a single instance by setting SWITCH_ON_EOI, which
+ * should cause IA to split instances up. However, this
+ * doesn't work correctly on SI when there is no other
+ * SE to switch to.
+ */
+ *num_patches = 1;
+ }
Hi Nicolai,
This commit massively decreases tessellation performance on SI 1-SE
parts. We need a different solution. Would this work: "Set num_patches
to the greatest divisor of the the number of patches per instance."
Yes, that should be sufficient. Actually, it'd be even better to only do
the workaround when PRIM_ID is read, which is probably quite rare...
Do you already have a patch for the first part?
Thanks,
Nicolai
--
Lerne, wie die Welt wirklich ist,
Aber vergiss niemals, wie sie sein sollte.
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