While we're here, we also make the two support checks static since there are no users outside intel_mipmap_tree.c. --- src/mesa/drivers/dri/i965/brw_blorp.c | 2 +- src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 45 +++++++++++++-------------- src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 18 ++--------- 3 files changed, 25 insertions(+), 40 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c b/src/mesa/drivers/dri/i965/brw_blorp.c index e8993a8..00092ee 100644 --- a/src/mesa/drivers/dri/i965/brw_blorp.c +++ b/src/mesa/drivers/dri/i965/brw_blorp.c @@ -785,7 +785,7 @@ do_single_blorp_clear(struct brw_context *brw, struct gl_framebuffer *fb, */ if (!irb->mt->mcs_buf) { assert(!intel_miptree_is_lossless_compressed(brw, irb->mt)); - if (!intel_miptree_alloc_non_msrt_mcs(brw, irb->mt, false)) { + if (!intel_miptree_alloc_ccs(brw, irb->mt, false)) { /* MCS allocation failed--probably this will only happen in * out-of-memory conditions. But in any case, try to recover * by falling back to a non-blorp clear technique. diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c index 3dddfae..0f6d542 100644 --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c @@ -101,9 +101,8 @@ compute_msaa_layout(struct brw_context *brw, mesa_format format, } } -bool -intel_tiling_supports_non_msrt_mcs(const struct brw_context *brw, - unsigned tiling) +static bool +intel_tiling_supports_ccs(const struct brw_context *brw, unsigned tiling) { /* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render * Target(s)", beneath the "Fast Color Clear" bullet (p326): @@ -141,9 +140,9 @@ intel_tiling_supports_non_msrt_mcs(const struct brw_context *brw, * - MCS and Lossless compression is supported for TiledY/TileYs/TileYf * non-MSRTs only. */ -bool -intel_miptree_supports_non_msrt_fast_clear(struct brw_context *brw, - const struct intel_mipmap_tree *mt) +static bool +intel_miptree_supports_ccs(struct brw_context *brw, + const struct intel_mipmap_tree *mt) { /* MCS support does not exist prior to Gen7 */ if (brw->gen < 7) @@ -243,9 +242,9 @@ intel_miptree_is_lossless_compressed(const struct brw_context *brw, return mt->num_samples <= 1; } -bool -intel_miptree_supports_lossless_compressed(struct brw_context *brw, - const struct intel_mipmap_tree *mt) +static bool +intel_miptree_supports_ccs_e(struct brw_context *brw, + const struct intel_mipmap_tree *mt) { /* For now compression is only enabled for integer formats even though * there exist supported floating point formats also. This is a heuristic @@ -257,8 +256,7 @@ intel_miptree_supports_lossless_compressed(struct brw_context *brw, if (_mesa_get_format_datatype(mt->format) == GL_FLOAT) return false; - /* Fast clear mechanism and lossless compression go hand in hand. */ - if (!intel_miptree_supports_non_msrt_fast_clear(brw, mt)) + if (!intel_miptree_supports_ccs(brw, mt)) return false; /* Fast clear can be also used to clear srgb surfaces by using equivalent @@ -512,7 +510,7 @@ intel_miptree_create_layout(struct brw_context *brw, * 7 | ? | ? * 6 | ? | ? */ - if (intel_miptree_supports_non_msrt_fast_clear(brw, mt)) { + if (intel_miptree_supports_ccs(brw, mt)) { if (brw->gen >= 9 || (brw->gen == 8 && num_samples <= 1)) layout_flags |= MIPTREE_LAYOUT_FORCE_HALIGN16; } else if (brw->gen >= 9 && num_samples > 1) { @@ -734,8 +732,8 @@ intel_miptree_create(struct brw_context *brw, * clear actually occurs or when compressed single sampled buffer is * written by the GPU for the first time. */ - if (intel_tiling_supports_non_msrt_mcs(brw, mt->tiling) && - intel_miptree_supports_non_msrt_fast_clear(brw, mt)) { + if (intel_tiling_supports_ccs(brw, mt->tiling) && + intel_miptree_supports_ccs(brw, mt)) { mt->aux_disable &= ~INTEL_AUX_DISABLE_CCS; assert(brw->gen < 8 || mt->halign == 16 || num_samples <= 1); @@ -747,10 +745,10 @@ intel_miptree_create(struct brw_context *brw, const bool is_lossless_compressed = unlikely(!lossless_compression_disabled) && brw->gen >= 9 && !mt->is_scanout && - intel_miptree_supports_lossless_compressed(brw, mt); + intel_miptree_supports_ccs_e(brw, mt); if (is_lossless_compressed) { - intel_miptree_alloc_non_msrt_mcs(brw, mt, is_lossless_compressed); + intel_miptree_alloc_ccs(brw, mt, is_lossless_compressed); } } @@ -856,8 +854,8 @@ intel_update_winsys_renderbuffer_miptree(struct brw_context *intel, * Allocation of the MCS miptree will be deferred until the first fast * clear actually occurs. */ - if (intel_tiling_supports_non_msrt_mcs(intel, singlesample_mt->tiling) && - intel_miptree_supports_non_msrt_fast_clear(intel, singlesample_mt)) { + if (intel_tiling_supports_ccs(intel, singlesample_mt->tiling) && + intel_miptree_supports_ccs(intel, singlesample_mt)) { singlesample_mt->aux_disable &= ~INTEL_AUX_DISABLE_CCS; } @@ -1552,9 +1550,9 @@ intel_miptree_alloc_mcs(struct brw_context *brw, } bool -intel_miptree_alloc_non_msrt_mcs(struct brw_context *brw, - struct intel_mipmap_tree *mt, - bool is_lossless_compressed) +intel_miptree_alloc_ccs(struct brw_context *brw, + struct intel_mipmap_tree *mt, + bool is_ccs_e) { assert(mt->mcs_buf == NULL); assert(!(mt->aux_disable & (INTEL_AUX_DISABLE_MCS | INTEL_AUX_DISABLE_CCS))); @@ -1592,8 +1590,7 @@ intel_miptree_alloc_non_msrt_mcs(struct brw_context *brw, * not use the gpu access flag which can cause an unnecessary delay if the * backing pages happened to be just used by the GPU. */ - const uint32_t alloc_flags = - is_lossless_compressed ? 0 : BO_ALLOC_FOR_RENDER; + const uint32_t alloc_flags = is_ccs_e ? 0 : BO_ALLOC_FOR_RENDER; buf->bo = brw_bo_alloc_tiled(brw->bufmgr, "ccs-miptree", buf->size, I915_TILING_Y, buf->pitch, alloc_flags); @@ -1610,7 +1607,7 @@ intel_miptree_alloc_non_msrt_mcs(struct brw_context *brw, * used for lossless compression which requires similar initialisation * as multi-sample compression. */ - if (is_lossless_compressed) { + if (is_ccs_e) { /* Hardware sets the auxiliary buffer to all zeroes when it does full * resolve. Initialize it accordingly in case the first renderer is * cpu (or other none compression aware party). diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h index f7b8e67..aa33967 100644 --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h @@ -654,21 +654,9 @@ intel_miptree_is_lossless_compressed(const struct brw_context *brw, const struct intel_mipmap_tree *mt); bool -intel_tiling_supports_non_msrt_mcs(const struct brw_context *brw, - unsigned tiling); - -bool -intel_miptree_supports_non_msrt_fast_clear(struct brw_context *brw, - const struct intel_mipmap_tree *mt); - -bool -intel_miptree_supports_lossless_compressed(struct brw_context *brw, - const struct intel_mipmap_tree *mt); - -bool -intel_miptree_alloc_non_msrt_mcs(struct brw_context *brw, - struct intel_mipmap_tree *mt, - bool is_lossless_compressed); +intel_miptree_alloc_ccs(struct brw_context *brw, + struct intel_mipmap_tree *mt, + bool is_ccs_e); enum { MIPTREE_LAYOUT_ACCELERATED_UPLOAD = 1 << 0, -- 2.5.0.400.gff86faf _______________________________________________ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev