Reviewed-by: Jason Ekstrand <ja...@jlekstrand.net> On Tue, Jul 18, 2017 at 1:46 AM, Topi Pohjolainen < topi.pohjolai...@gmail.com> wrote:
> Depth buffers are always Y-tiled. In brw_miptree_choose_tiling() > driver opts to use linear buffers for small and 1D but this does > not apply for depth - GL_DEPTH_COMPONENT and GL_DEPTH_STENCIL_EXT > are considered first. > > Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> > --- > src/mesa/drivers/dri/i965/brw_misc_state.c | 3 +-- > src/mesa/drivers/dri/i965/gen6_depth_state.c | 3 +-- > 2 files changed, 2 insertions(+), 4 deletions(-) > > diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c > b/src/mesa/drivers/dri/i965/brw_misc_state.c > index 0c43d2b4b2..1e3be784c5 100644 > --- a/src/mesa/drivers/dri/i965/brw_misc_state.c > +++ b/src/mesa/drivers/dri/i965/brw_misc_state.c > @@ -383,8 +383,7 @@ brw_emit_depth_stencil_hiz(struct brw_context *brw, > OUT_BATCH((depth_mt ? depth_mt->surf.row_pitch - 1 : 0) | > (depthbuffer_format << 18) | > (BRW_TILEWALK_YMAJOR << 26) | > - ((depth_mt ? depth_mt->surf.tiling != ISL_TILING_LINEAR : 1) > - << 27) | > + (1 << 27) | > (depth_surface_type << 29)); > > if (depth_mt) { > diff --git a/src/mesa/drivers/dri/i965/gen6_depth_state.c > b/src/mesa/drivers/dri/i965/gen6_depth_state.c > index 8f05b4cc1a..3e3d2c629b 100644 > --- a/src/mesa/drivers/dri/i965/gen6_depth_state.c > +++ b/src/mesa/drivers/dri/i965/gen6_depth_state.c > @@ -121,8 +121,7 @@ gen6_emit_depth_stencil_hiz(struct brw_context *brw, > ((enable_hiz_ss ? 1 : 0) << 21) | /* separate stencil enable > */ > ((enable_hiz_ss ? 1 : 0) << 22) | /* hiz enable */ > (BRW_TILEWALK_YMAJOR << 26) | > - ((depth_mt ? depth_mt->surf.tiling != ISL_TILING_LINEAR : 1) > - << 27) | > + (1 << 27) | > (surftype << 29)); > > /* 3DSTATE_DEPTH_BUFFER dw2 */ > -- > 2.11.0 > > _______________________________________________ > mesa-dev mailing list > mesa-dev@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/mesa-dev >
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