If we need to stall to read the bo, ask the GPU to copy it into the CPU cache whilst we wait. --- src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c index 3b5e5595d7..5cd8d24f1e 100644 --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c @@ -3421,6 +3421,18 @@ can_blit_slice(struct intel_mipmap_tree *mt, } static bool +map_will_stall(struct brw_bo *bo, GLbitfield mode) +{ + /* If we need to stall for reading the buffer, offload the cost + * of clflushing it to the GPU. + */ + if (!bo->cache_coherent && !(mode & GL_MAP_INVALIDATE_RANGE_BIT)) + mode |= GL_MAP_READ_BIT; + + return brw_bo_map_busy(bo, mode); +} + +static bool use_intel_mipree_map_blit(struct brw_context *brw, struct intel_mipmap_tree *mt, GLbitfield mode, @@ -3431,7 +3443,7 @@ use_intel_mipree_map_blit(struct brw_context *brw, * all the overhead involved. */ - if (!(mode & GL_MAP_WRITE_BIT) && + if (map_will_stall(mt->bo, mode) && !mt->compressed && (mt->surf.tiling == ISL_TILING_X || /* Prior to Sandybridge, the blitter can't handle Y tiling */ -- 2.13.3 _______________________________________________ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev