From: Marek Olšák <marek.ol...@amd.com>
---
src/gallium/drivers/radeonsi/si_pipe.c | 2 +-
src/gallium/drivers/radeonsi/si_shader_tgsi_alu.c | 14 ++++++++++++++
2 files changed, 15 insertions(+), 1 deletion(-)
diff --git a/src/gallium/drivers/radeonsi/si_pipe.c
b/src/gallium/drivers/radeonsi/si_pipe.c
index 82f0c58..fb65590 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.c
+++ b/src/gallium/drivers/radeonsi/si_pipe.c
@@ -737,40 +737,40 @@ static int si_get_shader_param(struct pipe_screen*
pscreen,
/* Supported boolean features. */
case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
case PIPE_SHADER_CAP_INTEGERS:
case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
+ case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
return 1;
case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
/* TODO: Indirect indexing of GS inputs is unimplemented. */
return shader != PIPE_SHADER_GEOMETRY &&
(sscreen->llvm_has_working_vgpr_indexing ||
/* TCS and TES load inputs directly from LDS or
* offchip memory, so indirect indexing is trivial. */
shader == PIPE_SHADER_TESS_CTRL ||
shader == PIPE_SHADER_TESS_EVAL);
case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
return sscreen->llvm_has_working_vgpr_indexing ||
/* TCS stores outputs directly to memory. */
shader == PIPE_SHADER_TESS_CTRL;
/* Unsupported boolean features. */
case PIPE_SHADER_CAP_SUBROUTINES:
case PIPE_SHADER_CAP_SUPPORTED_IRS:
- case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
return 0;
}
return 0;
}
static const struct nir_shader_compiler_options nir_options = {
.vertex_id_zero_based = true,
.lower_scmp = true,
.lower_flrp32 = true,
diff --git a/src/gallium/drivers/radeonsi/si_shader_tgsi_alu.c
b/src/gallium/drivers/radeonsi/si_shader_tgsi_alu.c
index 405469d..234fd7f 100644
--- a/src/gallium/drivers/radeonsi/si_shader_tgsi_alu.c
+++ b/src/gallium/drivers/radeonsi/si_shader_tgsi_alu.c
@@ -367,20 +367,25 @@ static void emit_ssg(const struct lp_build_tgsi_action
*action,
if (emit_data->inst->Instruction.Opcode == TGSI_OPCODE_I64SSG) {
cmp = LLVMBuildICmp(builder, LLVMIntSGT, emit_data->args[0],
bld_base->int64_bld.zero, "");
val = LLVMBuildSelect(builder, cmp, bld_base->int64_bld.one,
emit_data->args[0], "");
cmp = LLVMBuildICmp(builder, LLVMIntSGE, val,
bld_base->int64_bld.zero, "");
val = LLVMBuildSelect(builder, cmp, val,
LLVMConstInt(bld_base->int64_bld.elem_type, -1, true), "");
} else if (emit_data->inst->Instruction.Opcode == TGSI_OPCODE_ISSG) {
cmp = LLVMBuildICmp(builder, LLVMIntSGT, emit_data->args[0],
bld_base->int_bld.zero, "");
val = LLVMBuildSelect(builder, cmp, bld_base->int_bld.one,
emit_data->args[0], "");
cmp = LLVMBuildICmp(builder, LLVMIntSGE, val,
bld_base->int_bld.zero, "");
val = LLVMBuildSelect(builder, cmp, val,
LLVMConstInt(bld_base->int_bld.elem_type, -1, true), "");
+ } else if (emit_data->inst->Instruction.Opcode == TGSI_OPCODE_DSSG) {
+ cmp = LLVMBuildFCmp(builder, LLVMRealOGT, emit_data->args[0],
bld_base->dbl_bld.zero, "");
+ val = LLVMBuildSelect(builder, cmp, bld_base->dbl_bld.one,
emit_data->args[0], "");
+ cmp = LLVMBuildFCmp(builder, LLVMRealOGE, val,
bld_base->dbl_bld.zero, "");
+ val = LLVMBuildSelect(builder, cmp, val,
LLVMConstReal(bld_base->dbl_bld.elem_type, -1), "");
} else { // float SSG
cmp = LLVMBuildFCmp(builder, LLVMRealOGT, emit_data->args[0],
bld_base->base.zero, "");
val = LLVMBuildSelect(builder, cmp, bld_base->base.one,
emit_data->args[0], "");
cmp = LLVMBuildFCmp(builder, LLVMRealOGE, val,
bld_base->base.zero, "");
val = LLVMBuildSelect(builder, cmp, val,
LLVMConstReal(bld_base->base.elem_type, -1), "");
}
emit_data->output[emit_data->chan] = val;
}
@@ -738,33 +743,42 @@ void si_shader_context_init_alu(struct
lp_build_tgsi_context *bld_base)
bld_base->op_actions[TGSI_OPCODE_BFI].emit = emit_bfi;
bld_base->op_actions[TGSI_OPCODE_BREV].emit =
build_tgsi_intrinsic_nomem;
bld_base->op_actions[TGSI_OPCODE_BREV].intr_name =
"llvm.bitreverse.i32";
bld_base->op_actions[TGSI_OPCODE_CEIL].emit =
build_tgsi_intrinsic_nomem;
bld_base->op_actions[TGSI_OPCODE_CEIL].intr_name = "llvm.ceil.f32";
bld_base->op_actions[TGSI_OPCODE_CMP].emit = emit_cmp;
bld_base->op_actions[TGSI_OPCODE_COS].emit = build_tgsi_intrinsic_nomem;
bld_base->op_actions[TGSI_OPCODE_COS].intr_name = "llvm.cos.f32";
bld_base->op_actions[TGSI_OPCODE_DABS].emit =
build_tgsi_intrinsic_nomem;
bld_base->op_actions[TGSI_OPCODE_DABS].intr_name = "llvm.fabs.f64";
+ bld_base->op_actions[TGSI_OPCODE_DCEIL].emit =
build_tgsi_intrinsic_nomem;
+ bld_base->op_actions[TGSI_OPCODE_DCEIL].intr_name = "llvm.ceil.f64";
+ bld_base->op_actions[TGSI_OPCODE_DFLR].emit =
build_tgsi_intrinsic_nomem;
+ bld_base->op_actions[TGSI_OPCODE_DFLR].intr_name = "llvm.floor.f64";
bld_base->op_actions[TGSI_OPCODE_DFMA].emit =
build_tgsi_intrinsic_nomem;
bld_base->op_actions[TGSI_OPCODE_DFMA].intr_name = "llvm.fma.f64";
bld_base->op_actions[TGSI_OPCODE_DFRAC].emit = emit_frac;
bld_base->op_actions[TGSI_OPCODE_DIV].emit = emit_fdiv;
bld_base->op_actions[TGSI_OPCODE_DNEG].emit = emit_dneg;
+ bld_base->op_actions[TGSI_OPCODE_DROUND].emit =
build_tgsi_intrinsic_nomem;
+ bld_base->op_actions[TGSI_OPCODE_DROUND].intr_name = "llvm.rint.f64";
bld_base->op_actions[TGSI_OPCODE_DSEQ].emit = emit_dcmp;
bld_base->op_actions[TGSI_OPCODE_DSGE].emit = emit_dcmp;
bld_base->op_actions[TGSI_OPCODE_DSLT].emit = emit_dcmp;
bld_base->op_actions[TGSI_OPCODE_DSNE].emit = emit_dcmp;
+ bld_base->op_actions[TGSI_OPCODE_DSSG].emit = emit_ssg;
bld_base->op_actions[TGSI_OPCODE_DRSQ].emit =
build_tgsi_intrinsic_nomem;
bld_base->op_actions[TGSI_OPCODE_DRSQ].intr_name =
"llvm.amdgcn.rsq.f64";
bld_base->op_actions[TGSI_OPCODE_DSQRT].emit =
build_tgsi_intrinsic_nomem;
bld_base->op_actions[TGSI_OPCODE_DSQRT].intr_name = "llvm.sqrt.f64";
+ bld_base->op_actions[TGSI_OPCODE_DTRUNC].emit =
build_tgsi_intrinsic_nomem;
+ bld_base->op_actions[TGSI_OPCODE_DTRUNC].intr_name = "llvm.trunc.f64";
bld_base->op_actions[TGSI_OPCODE_EX2].emit = build_tgsi_intrinsic_nomem;
bld_base->op_actions[TGSI_OPCODE_EX2].intr_name = "llvm.exp2.f32";
bld_base->op_actions[TGSI_OPCODE_FLR].emit = build_tgsi_intrinsic_nomem;
bld_base->op_actions[TGSI_OPCODE_FLR].intr_name = "llvm.floor.f32";
bld_base->op_actions[TGSI_OPCODE_FMA].emit =
bld_base->op_actions[TGSI_OPCODE_MAD].emit;
bld_base->op_actions[TGSI_OPCODE_FRC].emit = emit_frac;
bld_base->op_actions[TGSI_OPCODE_F2I].emit = emit_f2i;
bld_base->op_actions[TGSI_OPCODE_F2U].emit = emit_f2u;
bld_base->op_actions[TGSI_OPCODE_FSEQ].emit = emit_fcmp;
--
2.7.4
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