From Intel PRM vol07, page 781 "5. Special Cases for Word Operations"
"There is a relaxed alignment rule for word destinations. When the
destination type is word (UW, W, HF), destination data types can be
aligned to either the lowest word or the second lowest word of the
execution channel. This means the destination data words can be
either all in the even word locations or all in the odd word
locations."
So word types required to be aligned to the 32-bit register. So
we need to allocate as minimum a full 32-bit register.
---
src/intel/compiler/brw_fs_builder.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/intel/compiler/brw_fs_builder.h
b/src/intel/compiler/brw_fs_builder.h
index 87394bc17b3..4ba3c0c7e0e 100644
--- a/src/intel/compiler/brw_fs_builder.h
+++ b/src/intel/compiler/brw_fs_builder.h
@@ -188,7 +188,7 @@ namespace brw {
if (n > 0)
return dst_reg(VGRF, shader->alloc.allocate(
- DIV_ROUND_UP(n * type_sz(type) *
dispatch_width(),
+ DIV_ROUND_UP(n * MAX2(4, type_sz(type)) *
dispatch_width(),
REG_SIZE)),
type);
else
--
2.11.0
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