On Mon, Sep 4, 2017 at 4:13 PM, Jan Vesely <jan.ves...@rutgers.edu> wrote: > On Sat, 2017-09-02 at 22:21 +0200, Erik Faye-Lund wrote: >> On Sat, Sep 2, 2017 at 2:55 AM, Jan Vesely <jan.ves...@rutgers.edu> wrote: >> > Denotes native half precision float operations capability >> > >> > Signed-off-by: Jan Vesely <jan.ves...@rutgers.edu> >> > --- >> > I can change the spelling to HALVES, but simplified english sounded more >> > appropriate. >> > >> > src/gallium/docs/source/screen.rst | 1 + >> > src/gallium/drivers/etnaviv/etnaviv_screen.c | 1 + >> > src/gallium/drivers/freedreno/freedreno_screen.c | 1 + >> > src/gallium/drivers/i915/i915_screen.c | 1 + >> > src/gallium/drivers/llvmpipe/lp_screen.c | 1 + >> > src/gallium/drivers/nouveau/nv30/nv30_screen.c | 1 + >> > src/gallium/drivers/nouveau/nv50/nv50_screen.c | 1 + >> > src/gallium/drivers/nouveau/nvc0/nvc0_screen.c | 1 + >> > src/gallium/drivers/r300/r300_screen.c | 1 + >> > src/gallium/drivers/r600/r600_pipe.c | 1 + >> > src/gallium/drivers/radeonsi/si_pipe.c | 1 + >> > src/gallium/drivers/softpipe/sp_screen.c | 1 + >> > src/gallium/drivers/svga/svga_screen.c | 1 + >> > src/gallium/drivers/swr/swr_screen.cpp | 1 + >> > src/gallium/drivers/vc4/vc4_screen.c | 1 + >> > src/gallium/drivers/virgl/virgl_screen.c | 1 + >> > src/gallium/include/pipe/p_defines.h | 1 + >> > 17 files changed, 17 insertions(+) >> > >> > diff --git a/src/gallium/docs/source/screen.rst >> > b/src/gallium/docs/source/screen.rst >> > index be14ddd0c0..e27a0e8325 100644 >> > --- a/src/gallium/docs/source/screen.rst >> > +++ b/src/gallium/docs/source/screen.rst >> > @@ -370,6 +370,7 @@ The integer capabilities: >> > * ``PIPE_CAP_TGSI_MUL_ZERO_WINS``: Whether TGSI shaders support the >> > ``TGSI_PROPERTY_MUL_ZERO_WINS`` shader property. >> > * ``PIPE_CAP_DOUBLES``: Whether double precision floating-point operations >> > +* ``PIPE_CAP_HALFS``: Whether half precision floating-point operations >> > are supported. >> > * ``PIPE_CAP_INT64``: Whether 64-bit integer operations are supported. >> > * ``PIPE_CAP_INT64_DIVMOD``: Whether 64-bit integer division/modulo >> > diff --git a/src/gallium/drivers/etnaviv/etnaviv_screen.c >> > b/src/gallium/drivers/etnaviv/etnaviv_screen.c >> > index f400e423de..9b4ff5bbf9 100644 >> > --- a/src/gallium/drivers/etnaviv/etnaviv_screen.c >> > +++ b/src/gallium/drivers/etnaviv/etnaviv_screen.c >> > @@ -248,6 +248,7 @@ etna_screen_get_param(struct pipe_screen *pscreen, >> > enum pipe_cap param) >> > case PIPE_CAP_TGSI_FS_FBFETCH: >> > case PIPE_CAP_TGSI_MUL_ZERO_WINS: >> > case PIPE_CAP_DOUBLES: >> > + case PIPE_CAP_HALFS: >> > case PIPE_CAP_INT64: >> > case PIPE_CAP_INT64_DIVMOD: >> > case PIPE_CAP_TGSI_TEX_TXF_LZ: >> >> Shouldn't this be a shader cap? Some GPUs only support FP16 in the >> fragment shader, for instance... > > Interesting, which GPUs would that be? I assumed that unified shaders > would prevent such differences between stages.
At least ARM Mali-400. A Gallium driver for it is currently in the works: - https://github.com/yuq/mesa-lima Tegra 2 also have differing precisions in the vertex and fragment shaders, but it's not even doing FP16, rather some unusual FP24 variant. _______________________________________________ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
