Would it be possible to use this workaround only when LS vertices > HS vertices? (which should be rare)
Marek On Mon, Sep 4, 2017 at 8:11 PM, Nicolai Hähnle <nhaeh...@gmail.com> wrote: > From: Nicolai Hähnle <nicolai.haeh...@amd.com> > > When the HS wave is empty, the hardware writes the LS VGPRs starting at > v0 instead of v2. Workaround by shifting them back into place when > necessary. For simplicity, this is always done in the LS prolog. > > According to the hardware team, this will be fixed in future chips, > so take that into account already. > > Note that this is not a bug fix, as the bug was already worked > around by commit 166823bfd26 ("radeonsi/gfx9: add a temporary workaround > for a tessellation driver bug"). This change merely replaces the > workaround by one that should be better. _______________________________________________ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev