On Mon, Sep 11, 2017 at 02:33:09PM +0200, Iago Toral Quiroga wrote:
> We were skipping this fallback for depth, but not for stencil
> which the hardware always requires to be W-tiled.
>
> Also, make the checks for whether we need to apply retiling
> strategies based on usage instead of tiling flags, which is
> safer and more explicit.
>
> This fixes a regression in a CTS test introduced with commit
> 4ea63fab77f0 that started applying re-tiling stencil surfaces
> in certain scenarios.
>
> v2: discard retiling based on usage fields instead of tiling
> flags. This is safer and more explicit.
>
> Fixes:
> KHR-GL45.direct_state_access.renderbuffers_storage
> ---
> src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 9 +++++----
> 1 file changed, 5 insertions(+), 4 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> index 79afdc5342..a431225918 100644
> --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> @@ -570,11 +570,12 @@ make_surface(struct brw_context *brw, GLenum target,
> mesa_format format,
> if (!isl_surf_init_s(&brw->isl_dev, &mt->surf, &init_info))
> goto fail;
>
> - /* In case caller doesn't specifically request Y-tiling (needed
> - * unconditionally for depth), check for corner cases needing special
> - * treatment.
> + /* Depth surfaces are always Y-tiled and stencil is always W-tiled. For
> + * everything else, check for corner cases needing special treatment.
> */
We also have Y-tiled copy of stencil on gen7 for texturing purposes (on gen7
hw can't sample W-tiled and in order to support stencil texturing we use the
copy). I wouldn't mind if the comment also mentioned this.
Reviewed-by: Topi Pohjolainen <topi.pohjolai...@intel.com>
> - if (tiling_flags & ~ISL_TILING_Y0_BIT) {
> + bool is_depth_stencil =
> + mt->surf.usage & (ISL_SURF_USAGE_STENCIL_BIT |
> ISL_SURF_USAGE_DEPTH_BIT);
> + if (!is_depth_stencil) {
> if (need_to_retile_as_linear(brw, mt->surf.row_pitch,
> mt->surf.tiling, mt->surf.samples)) {
> init_info.tiling_flags = 1u << ISL_TILING_LINEAR;
> --
> 2.11.0
>
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