On 09/12/2017 09:36 PM, Bas Nieuwenhuizen wrote:
On Tue, Sep 12, 2017 at 9:30 PM, Samuel Pitoiset
<samuel.pitoi...@gmail.com> wrote:
On 09/12/2017 09:16 PM, Bas Nieuwenhuizen wrote:
On Tue, Sep 12, 2017 at 9:13 PM, Samuel Pitoiset
<samuel.pitoi...@gmail.com> wrote:
On 09/12/2017 09:07 PM, Bas Nieuwenhuizen wrote:
On Tue, Sep 12, 2017 at 8:57 PM, Samuel Pitoiset
<samuel.pitoi...@gmail.com> wrote:
On 09/12/2017 08:12 PM, Bas Nieuwenhuizen wrote:
On Tue, Sep 12, 2017 at 12:35 PM, Samuel Pitoiset
<samuel.pitoi...@gmail.com> wrote:
Only the disassembly is currently dumped.
Signed-off-by: Samuel Pitoiset <samuel.pitoi...@gmail.com>
---
src/amd/vulkan/radv_debug.c | 78
++++++++++++++++++++++++++++++++++++++++++---
1 file changed, 73 insertions(+), 5 deletions(-)
diff --git a/src/amd/vulkan/radv_debug.c
b/src/amd/vulkan/radv_debug.c
index 0dc2d3a22b..fe9d9cfdba 100644
--- a/src/amd/vulkan/radv_debug.c
+++ b/src/amd/vulkan/radv_debug.c
@@ -76,13 +76,62 @@ radv_dump_trace(struct radv_device *device,
struct
radeon_winsys_cs *cs)
fclose(f);
}
+static void
+radv_dump_shader(struct radv_pipeline *pipeline, gl_shader_stage
stage,
FILE *f)
+{
+ struct radv_shader_variant *shader =
pipeline->shaders[stage];
+
+ if (!shader)
+ return;
+
+ fprintf(f, "%s:\n%s\n\n", radv_get_shader_name(shader,
stage),
+ shader->disasm_string);
+}
+
+static void
+radv_dump_shaders(struct radv_pipeline *pipeline, FILE *f)
+{
+ unsigned mask;
+
+ mask = pipeline->active_stages;
+ while (mask) {
+ int stage = u_bit_scan(&mask);
+
+ radv_dump_shader(pipeline, stage, f);
+ }
+
+ radv_dump_shader(pipeline, MESA_SHADER_COMPUTE, f);
+}
+
+static void
+radv_dump_state(struct radv_pipeline *pipeline, FILE *f)
+{
+ if (!pipeline)
+ return;
+
+ radv_dump_shaders(pipeline, f);
+}
+
+static struct radv_pipeline *
+radv_get_saved_graphics_pipeline(struct radv_device *device)
+{
+ uint64_t *ptr = (uint64_t *)device->trace_id_ptr;
+
+ return (struct radv_pipeline *)ptr[1];
+}
+
+static struct radv_pipeline *
+radv_get_saved_compute_pipeline(struct radv_device *device)
+{
+ uint64_t *ptr = (uint64_t *)device->trace_id_ptr;
+
+ return (struct radv_pipeline *)ptr[2];
+}
+
static bool
-radv_gpu_hang_occured(struct radv_queue *queue)
+radv_gpu_hang_occured(struct radv_queue *queue, enum ring_type ring)
{
struct radeon_winsys *ws = queue->device->ws;
- enum ring_type ring;
-
- ring = radv_queue_family_to_ring(queue->queue_family_index);
if (!ws->ctx_wait_idle(queue->hw_ctx, ring,
queue->queue_idx))
return true;
@@ -93,10 +142,14 @@ radv_gpu_hang_occured(struct radv_queue *queue)
void
radv_check_gpu_hangs(struct radv_queue *queue, struct
radeon_winsys_cs
*cs)
{
+ struct radv_pipeline *graphics_pipeline, *compute_pipeline;
struct radv_device *device = queue->device;
+ enum ring_type ring;
uint64_t addr;
- bool hang_occurred = radv_gpu_hang_occured(queue);
+ ring = radv_queue_family_to_ring(queue->queue_family_index);
+
+ bool hang_occurred = radv_gpu_hang_occured(queue, ring);
bool vm_fault_occurred = false;
if (queue->device->instance->debug_flags &
RADV_DEBUG_VM_FAULTS)
vm_fault_occurred =
ac_vm_fault_occured(device->physical_device->rad_info.chip_class,
@@ -104,11 +157,26 @@ radv_check_gpu_hangs(struct radv_queue *queue,
struct radeon_winsys_cs *cs)
if (!hang_occurred && !vm_fault_occurred)
return;
+ graphics_pipeline = radv_get_saved_graphics_pipeline(device);
+ compute_pipeline = radv_get_saved_compute_pipeline(device);
+
if (vm_fault_occurred) {
fprintf(stderr, "VM fault report.\n\n");
fprintf(stderr, "Failing VM page:
0x%08"PRIx64"\n\n",
addr);
}
+ switch (ring) {
+ case RING_GFX:
+ radv_dump_state(graphics_pipeline, stderr);
You may also need to dump the compute shader if set, as we can do
compute dispatches from the gfx ring.
The compute shader (if present) is already dumped in
radv_dump_shaders()
which is similar for all rings.
That dumps the compute shader of the graphics pipeline though? (which
will always be NULL). You need the compute shader of the compute
pipeline, even in the gfx ring.
Ah, pipeline->shaders[MESA_SHADER_COMPUTE] is always NULL in the the gfx
ring? I didn't notice that.
Its not the ring that matters, its the pipeline. We have gfx pipelines
and compute pipelines. the gfx pipelines will never have a compute
shader, and the compute pipelines only a compute shader. The gfx bind
point of the command buffer contains a gfx pipeline and the compute
bind point a compute pipeline, note that these can be different
pipelines. Note that on the gfx queue, both bind points exist, on the
compute queue only the compute bind point.
Okay, so cmd_buffer->compute_pipeline->shaders[MESA_SHADER_COMPUTE] is the
shader I have to dump, correct?
cmd_buffer->state.emitted_compute_pipeline->shaders[MESA_SHADER_COMPUTE]
should be the one.
Yeah, it's similar to radv_get_saved_compute_pipeline() then.
+ break;
+ case RING_COMPUTE:
+ radv_dump_state(compute_pipeline, stderr);
+ break;
+ default:
+ assert(0);
+ break;
+ }
+
radv_dump_trace(queue->device, cs);
abort();
}
--
2.14.1
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