From: Marek Olšák <marek.ol...@amd.com>
---
src/gallium/drivers/radeonsi/si_shader.c | 24 +++++++++++------------
src/gallium/drivers/radeonsi/si_shader_internal.h | 2 +-
src/gallium/drivers/radeonsi/si_shader_tgsi_mem.c | 2 +-
3 files changed, 14 insertions(+), 14 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_shader.c
b/src/gallium/drivers/radeonsi/si_shader.c
index d012c19..213628f 100644
--- a/src/gallium/drivers/radeonsi/si_shader.c
+++ b/src/gallium/drivers/radeonsi/si_shader.c
@@ -713,41 +713,46 @@ static LLVMValueRef get_primitive_id(struct
si_shader_context *ctx,
return ctx->i32_0;
}
}
/**
* Return the value of tgsi_ind_register for indexing.
* This is the indirect index with the constant offset added to it.
*/
LLVMValueRef si_get_indirect_index(struct si_shader_context *ctx,
const struct tgsi_ind_register *ind,
+ unsigned addr_mul,
int rel_index)
{
struct gallivm_state *gallivm = &ctx->gallivm;
LLVMValueRef result;
result = ctx->addrs[ind->Index][ind->Swizzle];
result = LLVMBuildLoad(gallivm->builder, result, "");
+
+ if (addr_mul != 1)
+ result = LLVMBuildMul(gallivm->builder, result,
+ LLVMConstInt(ctx->i32, addr_mul, 0), "");
result = LLVMBuildAdd(gallivm->builder, result,
LLVMConstInt(ctx->i32, rel_index, 0), "");
return result;
}
/**
* Like si_get_indirect_index, but restricts the return value to a (possibly
* undefined) value inside [0..num).
*/
LLVMValueRef si_get_bounded_indirect_index(struct si_shader_context *ctx,
const struct tgsi_ind_register *ind,
int rel_index, unsigned num)
{
- LLVMValueRef result = si_get_indirect_index(ctx, ind, rel_index);
+ LLVMValueRef result = si_get_indirect_index(ctx, ind, 1, rel_index);
return si_llvm_bound_index(ctx, result, num);
}
/**
* Calculate a dword address given an input or output register and a stride.
*/
static LLVMValueRef get_dw_address(struct si_shader_context *ctx,
const struct tgsi_full_dst_register *dst,
@@ -774,21 +779,21 @@ static LLVMValueRef get_dw_address(struct
si_shader_context *ctx,
} else
reg = *dst;
/* If the register is 2-dimensional (e.g. an array of vertices
* in a primitive), calculate the base address of the vertex. */
if (reg.Register.Dimension) {
LLVMValueRef index;
if (reg.Dimension.Indirect)
index = si_get_indirect_index(ctx, ®.DimIndirect,
- reg.Dimension.Index);
+ 1, reg.Dimension.Index);
else
index = LLVMConstInt(ctx->i32, reg.Dimension.Index, 0);
base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
LLVMBuildMul(gallivm->builder, index,
vertex_dw_stride, ""),
"");
}
/* Get information about the register. */
if (reg.Register.File == TGSI_FILE_INPUT) {
@@ -807,21 +812,21 @@ static LLVMValueRef get_dw_address(struct
si_shader_context *ctx,
if (reg.Register.Indirect) {
/* Add the relative address of the element. */
LLVMValueRef ind_index;
if (reg.Indirect.ArrayID)
first = array_first[reg.Indirect.ArrayID];
else
first = reg.Register.Index;
ind_index = si_get_indirect_index(ctx, ®.Indirect,
- reg.Register.Index - first);
+ 1, reg.Register.Index -
first);
base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
LLVMBuildMul(gallivm->builder, ind_index,
LLVMConstInt(ctx->i32, 4, 0),
""), "");
param = reg.Register.Dimension ?
si_shader_io_get_unique_index(name[first],
index[first]) :
si_shader_io_get_unique_index_patch(name[first],
index[first]);
} else {
param = reg.Register.Dimension ?
@@ -910,21 +915,21 @@ static LLVMValueRef get_tcs_tes_buffer_address_from_reg(
LLVMValueRef vertex_index = NULL;
LLVMValueRef param_index = NULL;
unsigned param_index_base, param_base;
reg = src ? *src : tgsi_full_src_register_from_dst(dst);
if (reg.Register.Dimension) {
if (reg.Dimension.Indirect)
vertex_index = si_get_indirect_index(ctx,
®.DimIndirect,
- reg.Dimension.Index);
+ 1,
reg.Dimension.Index);
else
vertex_index = LLVMConstInt(ctx->i32,
reg.Dimension.Index, 0);
}
/* Get information about the register. */
if (reg.Register.File == TGSI_FILE_INPUT) {
name = info->input_semantic_name;
index = info->input_semantic_index;
array_first = info->input_array_first;
} else if (reg.Register.File == TGSI_FILE_OUTPUT) {
@@ -936,21 +941,21 @@ static LLVMValueRef get_tcs_tes_buffer_address_from_reg(
return NULL;
}
if (reg.Register.Indirect) {
if (reg.Indirect.ArrayID)
param_base = array_first[reg.Indirect.ArrayID];
else
param_base = reg.Register.Index;
param_index = si_get_indirect_index(ctx, ®.Indirect,
- reg.Register.Index -
param_base);
+ 1, reg.Register.Index -
param_base);
} else {
param_base = reg.Register.Index;
param_index = ctx->i32_0;
}
param_index_base = reg.Register.Dimension ?
si_shader_io_get_unique_index(name[param_base],
index[param_base]) :
si_shader_io_get_unique_index_patch(name[param_base],
index[param_base]);
@@ -1904,21 +1909,20 @@ load_ssbo(struct ac_shader_abi *abi, LLVMValueRef
index, bool write)
return ac_build_indexed_load_const(&ctx->ac, rsrc_ptr, index);
}
static LLVMValueRef fetch_constant(
struct lp_build_tgsi_context *bld_base,
const struct tgsi_full_src_register *reg,
enum tgsi_opcode_type type,
unsigned swizzle)
{
struct si_shader_context *ctx = si_shader_context(bld_base);
- struct lp_build_context *base = &bld_base->base;
const struct tgsi_ind_register *ireg = ®->Indirect;
unsigned buf, idx;
LLVMValueRef addr, bufp;
LLVMValueRef result;
if (swizzle == LP_CHAN_ALL) {
unsigned chan;
LLVMValueRef values[4];
for (chan = 0; chan < TGSI_NUM_CHANNELS; ++chan)
@@ -1937,25 +1941,21 @@ static LLVMValueRef fetch_constant(
index = si_get_bounded_indirect_index(ctx, ®->DimIndirect,
reg->Dimension.Index,
ctx->num_const_buffers);
index = LLVMBuildAdd(ctx->gallivm.builder, index,
LLVMConstInt(ctx->i32,
SI_NUM_SHADER_BUFFERS, 0), "");
bufp = ac_build_indexed_load_const(&ctx->ac, ptr, index);
} else
bufp = load_const_buffer_desc(ctx, buf);
if (reg->Register.Indirect) {
- addr = ctx->addrs[ireg->Index][ireg->Swizzle];
- addr = LLVMBuildLoad(base->gallivm->builder, addr, "load addr
reg");
- addr = lp_build_mul_imm(&bld_base->uint_bld, addr, 16);
- addr = lp_build_add(&bld_base->uint_bld, addr,
- LLVMConstInt(ctx->i32, idx * 4, 0));
+ addr = si_get_indirect_index(ctx, ireg, 16, idx * 4);
} else {
addr = LLVMConstInt(ctx->i32, idx * 4, 0);
}
result = buffer_load_const(ctx, bufp, addr);
if (!tgsi_type_is_64bit(type))
result = bitcast(bld_base, type, result);
else {
LLVMValueRef addr2, result2;
@@ -3780,21 +3780,21 @@ static void build_interp_intrinsic(const struct
lp_build_tgsi_action *action,
if (array_id) {
input_base = info->input_array_first[array_id];
input_array_size = info->input_array_last[array_id] -
input_base + 1;
} else {
input_base = inst->Src[0].Register.Index;
input_array_size = info->num_inputs - input_base;
}
array_idx = si_get_indirect_index(ctx, &input->Indirect,
- input->Register.Index -
input_base);
+ 1, input->Register.Index -
input_base);
} else {
input_base = inst->Src[0].Register.Index;
input_array_size = 1;
array_idx = ctx->i32_0;
}
interp = shader->selector->info.input_interpolate[input_base];
if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE)
diff --git a/src/gallium/drivers/radeonsi/si_shader_internal.h
b/src/gallium/drivers/radeonsi/si_shader_internal.h
index 141dd34..932e457 100644
--- a/src/gallium/drivers/radeonsi/si_shader_internal.h
+++ b/src/gallium/drivers/radeonsi/si_shader_internal.h
@@ -294,21 +294,21 @@ void si_llvm_emit_store(struct lp_build_tgsi_context
*bld_base,
/* Combine these with & instead of |. */
#define NOOP_WAITCNT 0xf7f
#define LGKM_CNT 0x07f
#define VM_CNT 0xf70
void si_emit_waitcnt(struct si_shader_context *ctx, unsigned simm16);
LLVMValueRef si_get_indirect_index(struct si_shader_context *ctx,
const struct tgsi_ind_register *ind,
- int rel_index);
+ unsigned addr_mul, int rel_index);
LLVMValueRef si_get_bounded_indirect_index(struct si_shader_context *ctx,
const struct tgsi_ind_register *ind,
int rel_index, unsigned num);
LLVMTypeRef si_const_array(LLVMTypeRef elem_type, int num_elements);
void si_shader_context_init_alu(struct lp_build_tgsi_context *bld_base);
void si_shader_context_init_mem(struct si_shader_context *ctx);
LLVMValueRef si_load_sampler_desc(struct si_shader_context *ctx,
diff --git a/src/gallium/drivers/radeonsi/si_shader_tgsi_mem.c
b/src/gallium/drivers/radeonsi/si_shader_tgsi_mem.c
index be92044..ba13d3b 100644
--- a/src/gallium/drivers/radeonsi/si_shader_tgsi_mem.c
+++ b/src/gallium/drivers/radeonsi/si_shader_tgsi_mem.c
@@ -75,21 +75,21 @@ static LLVMValueRef
shader_buffer_fetch_rsrc(struct si_shader_context *ctx,
const struct tgsi_full_src_register *reg,
bool ubo)
{
LLVMValueRef index;
if (!reg->Register.Indirect) {
index = LLVMConstInt(ctx->i32, reg->Register.Index, false);
} else {
index = si_get_indirect_index(ctx, ®->Indirect,
- reg->Register.Index);
+ 1, reg->Register.Index);
}
if (ubo)
return ctx->abi.load_ubo(&ctx->abi, index);
else
return ctx->abi.load_ssbo(&ctx->abi, index, false);
}
static bool tgsi_is_array_sampler(unsigned target)
{
--
2.7.4
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