From: Marek Olšák <marek.ol...@amd.com>

---
 src/gallium/drivers/radeonsi/si_descriptors.c | 12 ++++--------
 1 file changed, 4 insertions(+), 8 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c 
b/src/gallium/drivers/radeonsi/si_descriptors.c
index a2b7c11..cac203b 100644
--- a/src/gallium/drivers/radeonsi/si_descriptors.c
+++ b/src/gallium/drivers/radeonsi/si_descriptors.c
@@ -123,22 +123,21 @@ static void si_init_descriptors(struct si_descriptors 
*desc,
        desc->shader_userdata_offset = shader_userdata_index * 4;
 }
 
 static void si_release_descriptors(struct si_descriptors *desc)
 {
        r600_resource_reference(&desc->buffer, NULL);
        FREE(desc->list);
 }
 
 static bool si_upload_descriptors(struct si_context *sctx,
-                                 struct si_descriptors *desc,
-                                 struct r600_atom * atom)
+                                 struct si_descriptors *desc)
 {
        unsigned slot_size = desc->element_dw_size * 4;
        unsigned first_slot_offset = desc->first_active_slot * slot_size;
        unsigned upload_size = desc->num_active_slots * slot_size;
 
        /* Skip the upload if no shader is using the descriptors. dirty_mask
         * will stay dirty and the descriptors will be uploaded when there is
         * a shader using them.
         */
        if (!upload_size)
@@ -156,23 +155,21 @@ static bool si_upload_descriptors(struct si_context *sctx,
        util_memcpy_cpu_to_le32(ptr, (char*)desc->list + first_slot_offset,
                                upload_size);
        desc->gpu_list = ptr - first_slot_offset / 4;
 
        radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, desc->buffer,
                             RADEON_USAGE_READ, RADEON_PRIO_DESCRIPTORS);
 
        /* The shader pointer should point to slot 0. */
        desc->buffer_offset -= first_slot_offset;
 
-       if (atom)
-               si_mark_atom_dirty(sctx, atom);
-
+       si_mark_atom_dirty(sctx, &sctx->shader_pointers.atom);
        return true;
 }
 
 static void
 si_descriptors_begin_new_cs(struct si_context *sctx, struct si_descriptors 
*desc)
 {
        if (!desc->buffer)
                return;
 
        radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, desc->buffer,
@@ -2149,21 +2146,21 @@ si_create_bindless_descriptor(struct si_context *sctx, 
uint32_t *desc_list,
         * 16-dword slots for now. Image descriptors only need 8-dword but this
         * doesn't really matter because no real apps use image handles.
         */
        desc_slot_offset = desc_slot * 16;
 
        /* Copy the descriptor into the array. */
        memcpy(desc->list + desc_slot_offset, desc_list, size);
 
        /* Re-upload the whole array of bindless descriptors into a new buffer.
         */
-       if (!si_upload_descriptors(sctx, desc, &sctx->shader_pointers.atom))
+       if (!si_upload_descriptors(sctx, desc))
                return 0;
 
        /* Make sure to re-emit the shader pointers for all stages. */
        sctx->graphics_bindless_pointer_dirty = true;
        sctx->compute_bindless_pointer_dirty = true;
 
        return desc_slot;
 }
 
 static void si_update_bindless_buffer_descriptor(struct si_context *sctx,
@@ -2622,22 +2619,21 @@ void si_init_all_descriptors(struct si_context *sctx)
 static bool si_upload_shader_descriptors(struct si_context *sctx, unsigned 
mask)
 {
        unsigned dirty = sctx->descriptors_dirty & mask;
 
        /* Assume nothing will go wrong: */
        sctx->shader_pointers_dirty |= dirty;
 
        while (dirty) {
                unsigned i = u_bit_scan(&dirty);
 
-               if (!si_upload_descriptors(sctx, &sctx->descriptors[i],
-                                          &sctx->shader_pointers.atom))
+               if (!si_upload_descriptors(sctx, &sctx->descriptors[i]))
                        return false;
        }
 
        sctx->descriptors_dirty &= ~mask;
 
        si_upload_bindless_descriptors(sctx);
 
        return true;
 }
 
-- 
2.7.4

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