On 14/10/17 09:49, Pohjolainen, Topi wrote: > On Thu, Oct 12, 2017 at 08:38:05PM +0200, Jose Maria Casanova Crespo wrote: >> From: Alejandro Piñeiro <apinhe...@igalia.com> >> >> Although it is possible to emit them directly as AND/OR on brw_fs_nir, >> having a specific opcode makes it easier to remove duplicate settings >> later. >> >> v2: (Curro) >> - Set thread control to 'switch' when using the control register >> - Use a single SHADER_OPCODE_RND_MODE opcode taking an immediate >> with the rounding mode. >> - Avoid magic numbers setting rounding mode field at control register. >> v3: (Curro) >> - Remove redundant and add missing whitespace lines. >> - Match printing instruction to IR opcode "rnd_mode" >> >> Signed-off-by: Alejandro Piñeiro <apinhe...@igalia.com> >> Signed-off-by: Jose Maria Casanova Crespo <jmcasan...@igalia.com> >> Reviewed-by: Francisco Jerez <curroje...@riseup.net> >> --- >> src/intel/compiler/brw_eu.h | 4 ++++ >> src/intel/compiler/brw_eu_defines.h | 16 ++++++++++++++++ >> src/intel/compiler/brw_eu_emit.c | 33 >> +++++++++++++++++++++++++++++++++ >> src/intel/compiler/brw_fs_generator.cpp | 5 +++++ >> src/intel/compiler/brw_shader.cpp | 4 ++++ >> 5 files changed, 62 insertions(+) >> >> diff --git a/src/intel/compiler/brw_eu.h b/src/intel/compiler/brw_eu.h >> index 8e597b212a..145942a54f 100644 >> --- a/src/intel/compiler/brw_eu.h >> +++ b/src/intel/compiler/brw_eu.h >> @@ -500,6 +500,10 @@ brw_broadcast(struct brw_codegen *p, >> struct brw_reg src, >> struct brw_reg idx); >> >> +void >> +brw_rounding_mode(struct brw_codegen *p, >> + enum brw_rnd_mode mode); >> + >> /*********************************************************************** >> * brw_eu_util.c: >> */ >> diff --git a/src/intel/compiler/brw_eu_defines.h >> b/src/intel/compiler/brw_eu_defines.h >> index da482b73c5..6687883bfb 100644 >> --- a/src/intel/compiler/brw_eu_defines.h >> +++ b/src/intel/compiler/brw_eu_defines.h >> @@ -388,6 +388,8 @@ enum opcode { >> SHADER_OPCODE_TYPED_SURFACE_WRITE, >> SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL, >> >> + SHADER_OPCODE_RND_MODE, >> + >> SHADER_OPCODE_MEMORY_FENCE, >> >> SHADER_OPCODE_GEN4_SCRATCH_READ, >> @@ -1214,4 +1216,18 @@ enum brw_message_target { >> /* R0 */ >> # define GEN7_GS_PAYLOAD_INSTANCE_ID_SHIFT 27 >> >> +/* CR0.0[5:4] Floating-Point Rounding Modes >> + * Skylake PRM, Volume 7 Part 1, "Control Register", page 756 >> + */ >> + >> +#define BRW_CR0_RND_MODE_MASK 0x30 >> +#define BRW_CR0_RND_MODE_SHIFT 4 >> + >> +enum PACKED brw_rnd_mode { >> + BRW_RND_MODE_RTNE = 0, /* Round to Nearest or Even */ >> + BRW_RND_MODE_RU = 1, /* Round Up, toward +inf */ >> + BRW_RND_MODE_RD = 2, /* Round Down, toward -inf */ >> + BRW_RND_MODE_RTZ = 3, /* Round Toward Zero */ >> +}; >> + >> #endif /* BRW_EU_DEFINES_H */ >> diff --git a/src/intel/compiler/brw_eu_emit.c >> b/src/intel/compiler/brw_eu_emit.c >> index 2b38d959d1..8c1e4c5eae 100644 >> --- a/src/intel/compiler/brw_eu_emit.c >> +++ b/src/intel/compiler/brw_eu_emit.c >> @@ -3450,3 +3450,36 @@ brw_WAIT(struct brw_codegen *p) >> brw_inst_set_exec_size(devinfo, insn, BRW_EXECUTE_1); >> brw_inst_set_mask_control(devinfo, insn, BRW_MASK_DISABLE); >> } >> + >> +/** >> + * Changes the floating point rounding mode updating the control register >> + * field defined at cr0.0[5-6] bits. This function supports the changes to >> + * RTNE (00), RU (01), RD (10) and RTZ (11) rounding using bitwise >> operations. >> + * Only RTNE and RTZ rounding are enabled at nir. >> + */ >> +void >> +brw_rounding_mode(struct brw_codegen *p, >> + enum brw_rnd_mode mode) >> +{ >> + const unsigned bits = mode << BRW_CR0_RND_MODE_SHIFT; > > Extra space before '='. >
Fixed locally Thanks. _______________________________________________ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev