On Mon, Oct 30, 2017 at 11:08 AM, Nanley Chery <nanleych...@gmail.com> wrote: > On Mon, Oct 02, 2017 at 04:08:00PM -0700, Anuj Phogat wrote: >> Cc: mesa-sta...@lists.freedesktop.org >> Signed-off-by: Anuj Phogat <anuj.pho...@gmail.com> >> --- >> src/mesa/drivers/dri/i965/brw_state_upload.c | 7 +++++-- >> 1 file changed, 5 insertions(+), 2 deletions(-) >> > > Assuming my comment in patch 3 is correct, we no longer have a need to > program this register. Therefore, we also don't need to implement this > workaround right?
I think we should still keep the workaround so that we don't miss it if we start making use of this register in future. We've to enable dw1 bit:6 for few CNL SKUs. Look at the bit description. > > -Nanley > >> diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c >> b/src/mesa/drivers/dri/i965/brw_state_upload.c >> index a1bf54dc72..c224355a2b 100644 >> --- a/src/mesa/drivers/dri/i965/brw_state_upload.c >> +++ b/src/mesa/drivers/dri/i965/brw_state_upload.c >> @@ -88,8 +88,11 @@ brw_upload_initial_gpu_state(struct brw_context *brw) >> if (devinfo->gen == 10) { >> BEGIN_BATCH(2); >> OUT_BATCH(_3DSTATE_3D_MODE << 16 | (2 - 2)); >> - OUT_BATCH(GEN10_FLOAT_BLEND_OPTIMIZATION_ENABLE << 16 | >> - GEN10_FLOAT_BLEND_OPTIMIZATION_ENABLE); >> + /* From gen10 workaround table in h/w specs: >> + * "On 3DSTATE_3D_MODE, driver must always program bits 31:16 of DW1 >> + * a value of 0xFFFF" >> + */ >> + OUT_BATCH(0xFFFF << 16 | GEN10_FLOAT_BLEND_OPTIMIZATION_ENABLE); >> ADVANCE_BATCH(); >> } >> >> -- >> 2.13.5 >> >> _______________________________________________ >> mesa-dev mailing list >> mesa-dev@lists.freedesktop.org >> https://lists.freedesktop.org/mailman/listinfo/mesa-dev _______________________________________________ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev