This patch should really be squashed in with the next one.
On Thu, Oct 12, 2017 at 11:38 AM, Jose Maria Casanova Crespo <
jmcasan...@igalia.com> wrote:
> From: Alejandro Piñeiro <apinhe...@igalia.com>
>
> ---
> src/intel/compiler/brw_fs_nir.cpp | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/src/intel/compiler/brw_fs_nir.cpp
> b/src/intel/compiler/brw_fs_nir.cpp
> index b356836e80..e108b5517b 100644
> --- a/src/intel/compiler/brw_fs_nir.cpp
> +++ b/src/intel/compiler/brw_fs_nir.cpp
> @@ -4056,11 +4056,10 @@ fs_visitor::nir_emit_intrinsic(const fs_builder
> &bld, nir_intrinsic_instr *instr
> * Also, we have to suffle 64-bit data to be in the appropriate
> layout
> * expected by our 32-bit write messages.
> */
> - unsigned type_size = 4;
> unsigned bit_size = instr->src[0].is_ssa ?
> instr->src[0].ssa->bit_size : instr->src[0].reg.reg->bit_size;
> + unsigned type_size = bit_size / 8;
> if (bit_size == 64) {
> - type_size = 8;
> fs_reg tmp =
> fs_reg(VGRF, alloc.allocate(alloc.sizes[val_reg.nr]),
> val_reg.type);
> shuffle_64bit_data_for_32bit_write(bld,
> @@ -4070,7 +4069,8 @@ fs_visitor::nir_emit_intrinsic(const fs_builder
> &bld, nir_intrinsic_instr *instr
> val_reg = tmp;
> }
>
> - unsigned type_slots = type_size / 4;
> + /* 16-bit types would use a minimum of 1 slot */
> + unsigned type_slots = MAX2(type_size / 4, 1);
>
> /* Combine groups of consecutive enabled channels in one write
> * message. We use ffs to find the first enabled channel and then
> ffs on
> --
> 2.13.6
>
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