[Mesa-dev] [PATCH 2/6] ac: use the ac i1 llvm type

[Timothy Arceri]

---
 src/amd/common/ac_nir_to_llvm.c | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index d792042925..9c01f0ad37 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -127,21 +127,20 @@ struct nir_to_llvm_context {
        LLVMValueRef esgs_ring;
        LLVMValueRef gsvs_ring;
        LLVMValueRef hs_ring_tess_offchip;
        LLVMValueRef hs_ring_tess_factor;
 
        LLVMValueRef prim_mask;
        LLVMValueRef sample_pos_offset;
        LLVMValueRef persp_sample, persp_center, persp_centroid;
        LLVMValueRef linear_sample, linear_center, linear_centroid;
 
-       LLVMTypeRef i1;
        LLVMTypeRef i8;
        LLVMTypeRef i16;
        LLVMTypeRef i64;
        LLVMTypeRef v2i32;
        LLVMTypeRef v3i32;
        LLVMTypeRef v4i32;
        LLVMTypeRef v8i32;
        LLVMTypeRef f64;
        LLVMTypeRef f32;
        LLVMTypeRef f16;
@@ -991,21 +990,20 @@ static void create_function(struct nir_to_llvm_context 
*ctx,
        default:
                unreachable("Shader stage not implemented");
        }
 
        ctx->shader_info->num_user_sgprs = user_sgpr_idx;
 }
 
 static void setup_types(struct nir_to_llvm_context *ctx)
 {
        ctx->voidt = LLVMVoidTypeInContext(ctx->context);
-       ctx->i1 = LLVMIntTypeInContext(ctx->context, 1);
        ctx->i8 = LLVMIntTypeInContext(ctx->context, 8);
        ctx->i16 = LLVMIntTypeInContext(ctx->context, 16);
        ctx->i64 = LLVMIntTypeInContext(ctx->context, 64);
        ctx->v2i32 = LLVMVectorType(ctx->ac.i32, 2);
        ctx->v3i32 = LLVMVectorType(ctx->ac.i32, 3);
        ctx->v4i32 = LLVMVectorType(ctx->ac.i32, 4);
        ctx->v8i32 = LLVMVectorType(ctx->ac.i32, 8);
        ctx->f32 = LLVMFloatTypeInContext(ctx->context);
        ctx->f16 = LLVMHalfTypeInContext(ctx->context);
        ctx->f64 = LLVMDoubleTypeInContext(ctx->context);
@@ -1336,21 +1334,21 @@ static LLVMValueRef emit_f2f16(struct 
nir_to_llvm_context *ctx,
        LLVMValueRef cond = NULL;
 
        src0 = ac_to_float(&ctx->ac, src0);
        result = LLVMBuildFPTrunc(ctx->builder, src0, ctx->f16, "");
 
        if (ctx->options->chip_class >= VI) {
                LLVMValueRef args[2];
                /* Check if the result is a denormal - and flush to 0 if so. */
                args[0] = result;
                args[1] = LLVMConstInt(ctx->ac.i32, N_SUBNORMAL | P_SUBNORMAL, 
false);
-               cond = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.class.f16", 
ctx->i1, args, 2, AC_FUNC_ATTR_READNONE);
+               cond = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.class.f16", 
ctx->ac.i1, args, 2, AC_FUNC_ATTR_READNONE);
        }
 
        /* need to convert back up to f32 */
        result = LLVMBuildFPExt(ctx->builder, result, ctx->f32, "");
 
        if (ctx->options->chip_class >= VI)
                result = LLVMBuildSelect(ctx->builder, cond, ctx->ac.f32_0, 
result, "");
        else {
                /* for SI/CIK */
                /* 0x38800000 is smallest half float value (2^-14) in 32-bit 
float,
-- 
2.14.3

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