From: Dave Airlie <airl...@redhat.com>
This moves some calculations of register values into the pipeline
construction, it saves looking at outinfo in the cmd buffer emit.
Signed-off-by: Dave Airlie <airl...@redhat.com>
---
src/amd/vulkan/radv_cmd_buffer.c | 29 ++++++++---------------------
src/amd/vulkan/radv_pipeline.c | 21 ++++++++++++++++++---
src/amd/vulkan/radv_private.h | 9 ++++++++-
3 files changed, 34 insertions(+), 25 deletions(-)
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index 6f5d4441ef6..cbd3f25d08e 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -698,28 +698,15 @@ radv_emit_shaders_prefetch(struct radv_cmd_buffer
*cmd_buffer,
static void
radv_emit_hw_vs(struct radv_cmd_buffer *cmd_buffer,
struct radv_pipeline *pipeline,
- struct radv_shader_variant *shader,
- struct ac_vs_output_info *outinfo)
+ struct radv_shader_variant *shader)
{
uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
- unsigned export_count;
- export_count = MAX2(1, outinfo->param_exports);
radeon_set_context_reg(cmd_buffer->cs, R_0286C4_SPI_VS_OUT_CONFIG,
- S_0286C4_VS_EXPORT_COUNT(export_count - 1));
+ pipeline->graphics.vs.spi_vs_out_config);
radeon_set_context_reg(cmd_buffer->cs, R_02870C_SPI_SHADER_POS_FORMAT,
-
S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
- S_02870C_POS1_EXPORT_FORMAT(outinfo->pos_exports
> 1 ?
-
V_02870C_SPI_SHADER_4COMP :
-
V_02870C_SPI_SHADER_NONE) |
- S_02870C_POS2_EXPORT_FORMAT(outinfo->pos_exports
> 2 ?
-
V_02870C_SPI_SHADER_4COMP :
-
V_02870C_SPI_SHADER_NONE) |
- S_02870C_POS3_EXPORT_FORMAT(outinfo->pos_exports
> 3 ?
-
V_02870C_SPI_SHADER_4COMP :
-
V_02870C_SPI_SHADER_NONE));
-
+ pipeline->graphics.vs.spi_shader_pos_format);
radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B120_SPI_SHADER_PGM_LO_VS, 4);
radeon_emit(cmd_buffer->cs, va >> 8);
@@ -735,11 +722,11 @@ radv_emit_hw_vs(struct radv_cmd_buffer *cmd_buffer,
radeon_set_context_reg(cmd_buffer->cs, R_02881C_PA_CL_VS_OUT_CNTL,
- pipeline->graphics.pa_cl_vs_out_cntl);
+ pipeline->graphics.vs.pa_cl_vs_out_cntl);
if (cmd_buffer->device->physical_device->rad_info.chip_class <= VI)
radeon_set_context_reg(cmd_buffer->cs, R_028AB4_VGT_REUSE_OFF,
-
S_028AB4_REUSE_OFF(outinfo->writes_viewport_index));
+ pipeline->graphics.vs.vgt_reuse_off);
}
static void
@@ -821,7 +808,7 @@ radv_emit_vertex_shader(struct radv_cmd_buffer *cmd_buffer,
else if (vs->info.vs.as_es)
radv_emit_hw_es(cmd_buffer, vs, &vs->info.vs.es_info);
else
- radv_emit_hw_vs(cmd_buffer, pipeline, vs, &vs->info.vs.outinfo);
+ radv_emit_hw_vs(cmd_buffer, pipeline, vs);
}
@@ -841,7 +828,7 @@ radv_emit_tess_shaders(struct radv_cmd_buffer *cmd_buffer,
if (tes->info.tes.as_es)
radv_emit_hw_es(cmd_buffer, tes,
&tes->info.tes.es_info);
else
- radv_emit_hw_vs(cmd_buffer, pipeline, tes,
&tes->info.tes.outinfo);
+ radv_emit_hw_vs(cmd_buffer, pipeline, tes);
}
radv_emit_hw_hs(cmd_buffer, tcs);
@@ -951,7 +938,7 @@ radv_emit_geometry_shader(struct radv_cmd_buffer
*cmd_buffer,
radeon_emit(cmd_buffer->cs, gs->rsrc2);
}
- radv_emit_hw_vs(cmd_buffer, pipeline, pipeline->gs_copy_shader,
&pipeline->gs_copy_shader->info.vs.outinfo);
+ radv_emit_hw_vs(cmd_buffer, pipeline, pipeline->gs_copy_shader);
struct ac_userdata_info *loc =
radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
AC_UD_GS_VS_RING_STRIDE_ENTRIES);
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index c6d9debc7e4..4a70ab53eb3 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -1545,7 +1545,7 @@ static void calculate_vgt_gs_mode(struct radv_pipeline
*pipeline)
}
}
-static void calculate_pa_cl_vs_out_cntl(struct radv_pipeline *pipeline)
+static void calculate_vs_outinfo(struct radv_pipeline *pipeline)
{
struct ac_vs_output_info *outinfo = get_vs_output_info(pipeline);
@@ -1557,7 +1557,7 @@ static void calculate_pa_cl_vs_out_cntl(struct
radv_pipeline *pipeline)
bool misc_vec_ena = outinfo->writes_pointsize ||
outinfo->writes_layer ||
outinfo->writes_viewport_index;
- pipeline->graphics.pa_cl_vs_out_cntl =
+ pipeline->graphics.vs.pa_cl_vs_out_cntl =
S_02881C_USE_VTX_POINT_SIZE(outinfo->writes_pointsize) |
S_02881C_USE_VTX_RENDER_TARGET_INDX(outinfo->writes_layer) |
S_02881C_USE_VTX_VIEWPORT_INDX(outinfo->writes_viewport_index) |
@@ -1568,6 +1568,21 @@ static void calculate_pa_cl_vs_out_cntl(struct
radv_pipeline *pipeline)
cull_dist_mask << 8 |
clip_dist_mask;
+ pipeline->graphics.vs.spi_shader_pos_format =
+ S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
+ S_02870C_POS1_EXPORT_FORMAT(outinfo->pos_exports > 1 ?
+ V_02870C_SPI_SHADER_4COMP :
+ V_02870C_SPI_SHADER_NONE) |
+ S_02870C_POS2_EXPORT_FORMAT(outinfo->pos_exports > 2 ?
+ V_02870C_SPI_SHADER_4COMP :
+ V_02870C_SPI_SHADER_NONE) |
+ S_02870C_POS3_EXPORT_FORMAT(outinfo->pos_exports > 3 ?
+ V_02870C_SPI_SHADER_4COMP :
+ V_02870C_SPI_SHADER_NONE);
+
+ pipeline->graphics.vs.spi_vs_out_config =
S_0286C4_VS_EXPORT_COUNT(MAX2(1, outinfo->param_exports) - 1);
+ /* only emitted on pre-VI */
+ pipeline->graphics.vs.vgt_reuse_off =
S_028AB4_REUSE_OFF(outinfo->writes_viewport_index);
}
static uint32_t offset_to_ps_input(uint32_t offset, bool flat_shade)
@@ -2051,7 +2066,7 @@ radv_pipeline_init(struct radv_pipeline *pipeline,
V_028710_SPI_SHADER_ZERO;
calculate_vgt_gs_mode(pipeline);
- calculate_pa_cl_vs_out_cntl(pipeline);
+ calculate_vs_outinfo(pipeline);
calculate_ps_inputs(pipeline);
for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
index cfbdfeb9909..c59c8b8a732 100644
--- a/src/amd/vulkan/radv_private.h
+++ b/src/amd/vulkan/radv_private.h
@@ -1110,6 +1110,13 @@ struct radv_vertex_elements_info {
uint32_t count;
};
+struct radv_vs_state {
+ uint32_t pa_cl_vs_out_cntl;
+ uint32_t spi_shader_pos_format;
+ uint32_t spi_vs_out_config;
+ uint32_t vgt_reuse_off;
+};
+
#define SI_GS_PER_ES 128
struct radv_pipeline {
@@ -1136,6 +1143,7 @@ struct radv_pipeline {
struct radv_multisample_state ms;
struct radv_tessellation_state tess;
struct radv_gs_state gs;
+ struct radv_vs_state vs;
uint32_t db_shader_control;
uint32_t shader_z_format;
unsigned prim;
@@ -1149,7 +1157,6 @@ struct radv_pipeline {
unsigned gsvs_ring_size;
uint32_t ps_input_cntl[32];
uint32_t ps_input_cntl_num;
- uint32_t pa_cl_vs_out_cntl;
uint32_t vgt_shader_stages_en;
uint32_t vtx_base_sgpr;
uint32_t base_ia_multi_vgt_param;
--
2.14.2
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