From: Dave Airlie <airl...@redhat.com>
This is ported from radeonsi and fixes:
dEQP-VK.pipeline.multisample_shader_builtin.sample_mask.bit_*
v2: don't call this path for radeonsi, it does it in the epilog.
use the radeonsi code path.
Signed-off-by: Dave Airlie <airl...@redhat.com>
---
src/amd/common/ac_nir_to_llvm.c | 29 ++++++++++++++++++++++++++++-
src/amd/common/ac_nir_to_llvm.h | 2 ++
src/amd/vulkan/radv_pipeline.c | 28 +++++++++++++++++++++++-----
src/amd/vulkan/radv_private.h | 2 ++
4 files changed, 55 insertions(+), 6 deletions(-)
diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index 214fb14..668cd50 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -4046,6 +4046,30 @@ static LLVMValueRef load_sample_pos(struct
ac_nir_context *ctx)
return ac_build_gather_values(&ctx->ac, values, 2);
}
+static LLVMValueRef load_sample_mask_in(struct ac_nir_context *ctx)
+{
+ uint8_t log2_ps_iter_samples =
ctx->nctx->shader_info->info.ps.force_persample ?
ctx->nctx->options->key.fs.log2_num_samples :
ctx->nctx->options->key.fs.log2_ps_iter_samples;
+
+ /* The bit pattern matches that used by fixed function fragment
+ * processing. */
+ static const uint16_t ps_iter_masks[] = {
+ 0xffff, /* not used */
+ 0x5555,
+ 0x1111,
+ 0x0101,
+ 0x0001,
+ };
+ assert(log2_ps_iter_samples < ARRAY_SIZE(ps_iter_masks));
+
+ uint32_t ps_iter_mask = ps_iter_masks[log2_ps_iter_samples];
+
+ LLVMValueRef result, sample_id;
+ sample_id = unpack_param(&ctx->ac, ctx->abi->ancillary, 8, 4);
+ sample_id = LLVMBuildShl(ctx->ac.builder, LLVMConstInt(ctx->ac.i32,
ps_iter_mask, false), sample_id, "");
+ result = LLVMBuildAnd(ctx->ac.builder, sample_id,
ctx->abi->sample_coverage, "");
+ return result;
+}
+
static LLVMValueRef visit_interp(struct nir_to_llvm_context *ctx,
const nir_intrinsic_instr *instr)
{
@@ -4350,7 +4374,10 @@ static void visit_intrinsic(struct ac_nir_context *ctx,
result = load_sample_pos(ctx);
break;
case nir_intrinsic_load_sample_mask_in:
- result = ctx->abi->sample_coverage;
+ if (ctx->nctx)
+ result = load_sample_mask_in(ctx);
+ else
+ result = ctx->abi->sample_coverage;
break;
case nir_intrinsic_load_frag_coord: {
LLVMValueRef values[4] = {
diff --git a/src/amd/common/ac_nir_to_llvm.h b/src/amd/common/ac_nir_to_llvm.h
index 62ea38b..1656289 100644
--- a/src/amd/common/ac_nir_to_llvm.h
+++ b/src/amd/common/ac_nir_to_llvm.h
@@ -60,6 +60,8 @@ struct ac_tcs_variant_key {
struct ac_fs_variant_key {
uint32_t col_format;
+ uint8_t log2_ps_iter_samples;
+ uint8_t log2_num_samples;
uint32_t is_int8;
uint32_t is_int10;
uint32_t multisample : 1;
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index f29c88e..98d1eca 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -798,6 +798,18 @@ radv_pipeline_init_raster_state(struct radv_pipeline
*pipeline,
}
+static uint8_t radv_pipeline_get_ps_iter_samples(const
VkGraphicsPipelineCreateInfo *pCreateInfo)
+{
+ uint32_t num_samples =
pCreateInfo->pMultisampleState->rasterizationSamples;
+ uint32_t ps_iter_samples = num_samples;
+
+ if (pCreateInfo->pMultisampleState->sampleShadingEnable) {
+ ps_iter_samples =
ceil(pCreateInfo->pMultisampleState->minSampleShading * num_samples);
+ ps_iter_samples = util_next_power_of_two(ps_iter_samples);
+ }
+ return ps_iter_samples;
+}
+
static void
radv_pipeline_init_multisample_state(struct radv_pipeline *pipeline,
const VkGraphicsPipelineCreateInfo
*pCreateInfo)
@@ -813,9 +825,8 @@ radv_pipeline_init_multisample_state(struct radv_pipeline
*pipeline,
else
ms->num_samples = 1;
- if (vkms && vkms->sampleShadingEnable) {
- ps_iter_samples = ceil(vkms->minSampleShading *
ms->num_samples);
- } else if
(pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.force_persample) {
+ ps_iter_samples = radv_pipeline_get_ps_iter_samples(pCreateInfo);
+ if (vkms && !vkms->sampleShadingEnable &&
pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.force_persample) {
ps_iter_samples = ms->num_samples;
}
@@ -838,7 +849,7 @@ radv_pipeline_init_multisample_state(struct radv_pipeline
*pipeline,
if (ms->num_samples > 1) {
unsigned log_samples = util_logbase2(ms->num_samples);
- unsigned log_ps_iter_samples =
util_logbase2(util_next_power_of_two(ps_iter_samples));
+ unsigned log_ps_iter_samples = util_logbase2(ps_iter_samples);
ms->pa_sc_mode_cntl_0 |= S_028A48_MSAA_ENABLE(1);
ms->pa_sc_line_cntl |= S_028BDC_EXPAND_LINE_WIDTH(1); /*
CM_R_028BDC_PA_SC_LINE_CNTL */
ms->db_eqaa |= S_028804_MAX_ANCHOR_SAMPLES(log_samples) |
@@ -1745,8 +1756,13 @@ radv_generate_graphics_pipeline_key(struct radv_pipeline
*pipeline,
if (pCreateInfo->pMultisampleState &&
- pCreateInfo->pMultisampleState->rasterizationSamples > 1)
+ pCreateInfo->pMultisampleState->rasterizationSamples > 1) {
+ uint32_t num_samples =
pCreateInfo->pMultisampleState->rasterizationSamples;
+ uint32_t ps_iter_samples =
radv_pipeline_get_ps_iter_samples(pCreateInfo);
key.multisample = true;
+ key.log2_num_samples = util_logbase2(num_samples);
+ key.log2_ps_iter_samples = util_logbase2(ps_iter_samples);
+ }
key.col_format = pipeline->graphics.blend.spi_shader_col_format;
if (pipeline->device->physical_device->rad_info.chip_class < VI)
@@ -1784,6 +1800,8 @@ radv_fill_shader_keys(struct ac_shader_variant_key *keys,
keys[MESA_SHADER_FRAGMENT].fs.col_format = key->col_format;
keys[MESA_SHADER_FRAGMENT].fs.is_int8 = key->is_int8;
keys[MESA_SHADER_FRAGMENT].fs.is_int10 = key->is_int10;
+ keys[MESA_SHADER_FRAGMENT].fs.log2_ps_iter_samples =
key->log2_ps_iter_samples;
+ keys[MESA_SHADER_FRAGMENT].fs.log2_num_samples = key->log2_num_samples;
}
static void
diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
index 1453b34..e754719 100644
--- a/src/amd/vulkan/radv_private.h
+++ b/src/amd/vulkan/radv_private.h
@@ -331,6 +331,8 @@ struct radv_pipeline_key {
uint32_t col_format;
uint32_t is_int8;
uint32_t is_int10;
+ uint8_t log2_ps_iter_samples;
+ uint8_t log2_num_samples;
uint32_t multisample : 1;
uint32_t has_multiview_view_index : 1;
};
--
2.9.5
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