From PIPE_CONTROL command description in gfxspecs: "Whenever a Binding Table Index (BTI) used by a Render Taget Message points to a different RENDER_SURFACE_STATE, SW must issue a Render Target Cache Flush by enabling this bit. When render target flush is set due to new association of BTI, PS Scoreboard Stall bit must be set in this packet."
Fixes a fulsim error and a GPU hang described in below JIRA. JIRA: MD5-322 Signed-off-by: Anuj Phogat <anuj.pho...@gmail.com> --- src/mesa/drivers/dri/i965/brw_binding_tables.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_binding_tables.c b/src/mesa/drivers/dri/i965/brw_binding_tables.c index 73f5e56010..170daebc24 100644 --- a/src/mesa/drivers/dri/i965/brw_binding_tables.c +++ b/src/mesa/drivers/dri/i965/brw_binding_tables.c @@ -93,6 +93,20 @@ brw_upload_binding_table(struct brw_context *brw, OUT_BATCH(stage_state->bind_bo_offset); ADVANCE_BATCH(); } + + /* From PIPE_CONTROL command description in gfxspecs: + + "Whenever a Binding Table Index (BTI) used by a Render Taget Message + points to a different RENDER_SURFACE_STATE, SW must issue a Render + Target Cache Flush by enabling this bit. When render target flush + is set due to new association of BTI, PS Scoreboard Stall bit must + be set in this packet." + */ + if (devinfo->gen >= 11) { + brw_emit_pipe_control_flush(brw, + PIPE_CONTROL_RENDER_TARGET_FLUSH | + PIPE_CONTROL_STALL_AT_SCOREBOARD); + } } /** -- 2.13.6 _______________________________________________ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev