---
src/intel/compiler/brw_fs_nir.cpp | 10 +++++++++-
src/intel/compiler/brw_vec4_nir.cpp | 4 ++++
2 files changed, 13 insertions(+), 1 deletion(-)
diff --git a/src/intel/compiler/brw_fs_nir.cpp
b/src/intel/compiler/brw_fs_nir.cpp
index 0d77564930..cf3df75cd5 100644
--- a/src/intel/compiler/brw_fs_nir.cpp
+++ b/src/intel/compiler/brw_fs_nir.cpp
@@ -1011,7 +1011,11 @@ fs_visitor::nir_emit_alu(const fs_builder &bld,
nir_alu_instr *instr)
case nir_op_flt:
case nir_op_fge:
case nir_op_feq:
- case nir_op_fne: {
+ case nir_op_fne:
+ case nir_op_uflt:
+ case nir_op_ufge:
+ case nir_op_ufeq:
+ case nir_op_ufne: {
fs_reg dest = result;
if (nir_src_bit_size(instr->src[0].src) > 32) {
dest = bld.vgrf(BRW_REGISTER_TYPE_DF, 1);
@@ -1019,15 +1023,19 @@ fs_visitor::nir_emit_alu(const fs_builder &bld,
nir_alu_instr *instr)
brw_conditional_mod cond;
switch (instr->op) {
case nir_op_flt:
+ case nir_op_uflt:
cond = BRW_CONDITIONAL_L;
break;
case nir_op_fge:
+ case nir_op_ufge:
cond = BRW_CONDITIONAL_GE;
break;
case nir_op_feq:
+ case nir_op_ufeq:
cond = BRW_CONDITIONAL_Z;
break;
case nir_op_fne:
+ case nir_op_ufne:
cond = BRW_CONDITIONAL_NZ;
break;
default:
diff --git a/src/intel/compiler/brw_vec4_nir.cpp
b/src/intel/compiler/brw_vec4_nir.cpp
index 7131fa06b4..1b50d4265a 100644
--- a/src/intel/compiler/brw_vec4_nir.cpp
+++ b/src/intel/compiler/brw_vec4_nir.cpp
@@ -967,16 +967,19 @@ brw_conditional_for_nir_comparison(nir_op op)
{
switch (op) {
case nir_op_flt:
+ case nir_op_uflt:
case nir_op_ilt:
case nir_op_ult:
return BRW_CONDITIONAL_L;
case nir_op_fge:
+ case nir_op_ufge:
case nir_op_ige:
case nir_op_uge:
return BRW_CONDITIONAL_GE;
case nir_op_feq:
+ case nir_op_ufeq:
case nir_op_ieq:
case nir_op_ball_fequal2:
case nir_op_ball_iequal2:
@@ -987,6 +990,7 @@ brw_conditional_for_nir_comparison(nir_op op)
return BRW_CONDITIONAL_Z;
case nir_op_fne:
+ case nir_op_ufne:
case nir_op_ine:
case nir_op_bany_fnequal2:
case nir_op_bany_inequal2:
--
2.14.3
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