On Thu, Feb 15, 2018 at 5:44 PM, Anuj Phogat <anuj.pho...@gmail.com> wrote:

> The PIPE_CONTROL command description says:
>
> "Whenever a Binding Table Index (BTI) used by a Render Taget Message
> points to a different RENDER_SURFACE_STATE, SW must issue a Render
> Target Cache Flush by enabling this bit. When render target flush
> is set due to new association of BTI, PS Scoreboard Stall bit must
> be set in this packet."
>
> Signed-off-by: Anuj Phogat <anuj.pho...@gmail.com>
> ---
>  src/intel/vulkan/genX_cmd_buffer.c | 21 +++++++++++++++++++++
>  1 file changed, 21 insertions(+)
>
> diff --git a/src/intel/vulkan/genX_cmd_buffer.c
> b/src/intel/vulkan/genX_cmd_buffer.c
> index ce47b8a1cc..e2b6c281e4 100644
> --- a/src/intel/vulkan/genX_cmd_buffer.c
> +++ b/src/intel/vulkan/genX_cmd_buffer.c
> @@ -2001,6 +2001,27 @@ emit_binding_table(struct anv_cmd_buffer
> *cmd_buffer,
>   out:
>     anv_state_flush(cmd_buffer->device, *bt_state);
>
> +#if GEN_GEN >= 11
> +   /* The PIPE_CONTROL command description says:
> +    *
> +    * "Whenever a Binding Table Index (BTI) used by a Render Taget Message
> +    *  points to a different RENDER_SURFACE_STATE, SW must issue a Render
> +    *  Target Cache Flush by enabling this bit. When render target flush
> +    *  is set due to new association of BTI, PS Scoreboard Stall bit must
> +    *  be set in this packet."
>

We usually indent block quotes like this.


> +    *
> +    *  FINISHME: Currently we shuffle around the surface states in the
> +    *  binding table based on if they are getting used or not. So, we've
> +    *  to do below pipe control flush for every binding table upload.
> +    *  Make changes so that we do it only when we modify render target
> +    *  surface states.
> +    */
> +   anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
> +      pc.RenderTargetCacheFlushEnable  = true;
> +      pc.StallAtPixelScoreboard        = true;
> +   }
> +#endif
> +
>     return VK_SUCCESS;
>  }
>
> --
> 2.13.6
>
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