On Mon, Feb 26, 2018 at 11:14:05AM -0800, Matt Turner wrote: > On Fri, Feb 23, 2018 at 5:18 AM, Thierry Reding > <thierry.red...@gmail.com> wrote: > > From: Thierry Reding <tred...@nvidia.com> > > > > The disk cache implementation uses 64-bit atomic operations. For some > > architectures, such as 32-bit ARM, GCC will not be able to translate > > these operations into lock-free instructions and will instead rely on > > Here, and in the comment in meson.build, I think you mean "atomic" > rather than "lock-free" instructions? It's at least confusing, since > on x86 atomic instructions have a "lock" prefix.
This uses the terminology used by the GCC documentation, see:
https://gcc.gnu.org/wiki/Atomic/GCCMM
I think the GCC terms merely mean that you don't need any explicit
locking for these operations to be atomic.
How about this instead:
"... operations into atomic, lock-free instructions..."
?
Thierry
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