On Wed, May 2, 2018 at 3:48 AM, Iago Toral Quiroga <ito...@igalia.com>
wrote:
> NIR assumes that booleans are always 32-bit, but Intel hardware produces
> 16-bit booleans for 16-bit comparisons. This means that we need to convert
> the 16-bit result to 32-bit.
>
> In the future we want to add an optimization pass to clean this up and
> hopefully remove the conversions.
>
> v2 (Jason): use the type of the source for the temporary and use
> brw_reg_type_from_bit_size for the conversion to 32-bit.
> ---
> src/intel/compiler/brw_fs_nir.cpp | 42 ++++++++++++++++++++++++++++++
> +--------
> 1 file changed, 34 insertions(+), 8 deletions(-)
>
> diff --git a/src/intel/compiler/brw_fs_nir.cpp
> b/src/intel/compiler/brw_fs_nir.cpp
> index b9d8ade4cf..f763dfa4f2 100644
> --- a/src/intel/compiler/brw_fs_nir.cpp
> +++ b/src/intel/compiler/brw_fs_nir.cpp
> @@ -1017,9 +1017,11 @@ fs_visitor::nir_emit_alu(const fs_builder &bld,
> nir_alu_instr *instr)
> case nir_op_feq:
> case nir_op_fne: {
> fs_reg dest = result;
> - if (nir_src_bit_size(instr->src[0].src) > 32) {
> - dest = bld.vgrf(BRW_REGISTER_TYPE_DF, 1);
> - }
> +
> + const uint32_t bit_size = nir_src_bit_size(instr->src[0].src);
> + if (bit_size != 32)
> + dest = bld.vgrf(op[0].type, 1);
> +
> brw_conditional_mod cond;
> switch (instr->op) {
> case nir_op_flt:
> @@ -1037,9 +1039,21 @@ fs_visitor::nir_emit_alu(const fs_builder &bld,
> nir_alu_instr *instr)
> default:
> unreachable("bad opcode");
> }
> +
> bld.CMP(dest, op[0], op[1], cond);
> - if (nir_src_bit_size(instr->src[0].src) > 32) {
> +
> + if (bit_size > 32) {
> bld.MOV(result, subscript(dest, BRW_REGISTER_TYPE_UD, 0));
> + } else if(bit_size < 32) {
> + /* When we convert the result to 32-bit we need to be careful
> and do
> + * it as a signed conversion to get sign extension (for 32-bit
> true)
> + */
> + const brw_reg_type dst_type =
> + brw_reg_type_from_bit_size(32, BRW_REGISTER_TYPE_D);
>
I think you can just use BRW_REGISTER_TYPE_D here. But whatever, this is
ok too.
Reviewed-by: Jason Ekstrand <ja...@jlekstrand.net>
> + const brw_reg_type src_type =
> + brw_reg_type_from_bit_size(bit_size, BRW_REGISTER_TYPE_D);
> +
> + bld.MOV(retype(result, dst_type), retype(dest, src_type));
> }
> break;
> }
> @@ -1051,9 +1065,10 @@ fs_visitor::nir_emit_alu(const fs_builder &bld,
> nir_alu_instr *instr)
> case nir_op_ieq:
> case nir_op_ine: {
> fs_reg dest = result;
> - if (nir_src_bit_size(instr->src[0].src) > 32) {
> - dest = bld.vgrf(BRW_REGISTER_TYPE_UQ, 1);
> - }
> +
> + const uint32_t bit_size = nir_src_bit_size(instr->src[0].src);
> + if (bit_size != 32)
> + dest = bld.vgrf(op[0].type, 1);
>
> brw_conditional_mod cond;
> switch (instr->op) {
> @@ -1075,8 +1090,19 @@ fs_visitor::nir_emit_alu(const fs_builder &bld,
> nir_alu_instr *instr)
> unreachable("bad opcode");
> }
> bld.CMP(dest, op[0], op[1], cond);
> - if (nir_src_bit_size(instr->src[0].src) > 32) {
> +
> + if (bit_size > 32) {
> bld.MOV(result, subscript(dest, BRW_REGISTER_TYPE_UD, 0));
> + } else if (bit_size < 32) {
> + /* When we convert the result to 32-bit we need to be careful
> and do
> + * it as a signed conversion to get sign extension (for 32-bit
> true)
> + */
> + const brw_reg_type dst_type =
> + brw_reg_type_from_bit_size(32, BRW_REGISTER_TYPE_D);
> + const brw_reg_type src_type =
> + brw_reg_type_from_bit_size(bit_size, BRW_REGISTER_TYPE_D);
> +
> + bld.MOV(retype(result, dst_type), retype(dest, src_type));
> }
> break;
> }
> --
> 2.14.1
>
>
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