From: Marek Olšák <marek.ol...@amd.com>
---
src/gallium/drivers/radeonsi/si_pipe.h | 17 +++++++++++++++++
src/gallium/drivers/radeonsi/si_state_draw.c | 11 +++--------
src/gallium/drivers/radeonsi/si_state_shaders.c | 6 ++----
.../drivers/radeonsi/si_state_viewport.c | 2 +-
4 files changed, 23 insertions(+), 13 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_pipe.h
b/src/gallium/drivers/radeonsi/si_pipe.h
index 6b181f6856a..62bb8afd63a 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.h
+++ b/src/gallium/drivers/radeonsi/si_pipe.h
@@ -1496,20 +1496,37 @@ static inline unsigned si_get_total_colormask(struct
si_context *sctx)
sctx->queued.named.blend->cb_target_mask;
if (!ps->info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS])
colormask &= ps->colors_written_4bit;
else if (!ps->colors_written_4bit)
colormask = 0; /* color0 writes all cbufs, but it's not written
*/
return colormask;
}
+#define UTIL_ALL_PRIM_LINE_MODES ((1 << PIPE_PRIM_LINES) | \
+ (1 << PIPE_PRIM_LINE_LOOP) | \
+ (1 << PIPE_PRIM_LINE_STRIP) | \
+ (1 << PIPE_PRIM_LINES_ADJACENCY) | \
+ (1 << PIPE_PRIM_LINE_STRIP_ADJACENCY))
+
+static inline bool util_prim_is_lines(unsigned prim)
+{
+ return ((1 << prim) & UTIL_ALL_PRIM_LINE_MODES) != 0;
+}
+
+static inline bool util_prim_is_points_or_lines(unsigned prim)
+{
+ return ((1 << prim) & (UTIL_ALL_PRIM_LINE_MODES |
+ (1 << PIPE_PRIM_POINTS))) != 0;
+}
+
/**
* Return true if there is enough memory in VRAM and GTT for the buffers
* added so far.
*
* \param vram VRAM memory size not added to the buffer list yet
* \param gtt GTT memory size not added to the buffer list yet
*/
static inline bool
radeon_cs_memory_below_limit(struct si_screen *screen,
struct radeon_winsys_cs *cs,
diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c
b/src/gallium/drivers/radeonsi/si_state_draw.c
index e33e235620a..5370587d747 100644
--- a/src/gallium/drivers/radeonsi/si_state_draw.c
+++ b/src/gallium/drivers/radeonsi/si_state_draw.c
@@ -514,25 +514,21 @@ static unsigned si_get_ia_multi_vgt_param(struct
si_context *sctx,
}
/* rast_prim is the primitive type after GS. */
static bool si_emit_rasterizer_prim_state(struct si_context *sctx)
{
struct radeon_winsys_cs *cs = sctx->gfx_cs;
enum pipe_prim_type rast_prim = sctx->current_rast_prim;
struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
/* Skip this if not rendering lines. */
- if (rast_prim != PIPE_PRIM_LINES &&
- rast_prim != PIPE_PRIM_LINE_LOOP &&
- rast_prim != PIPE_PRIM_LINE_STRIP &&
- rast_prim != PIPE_PRIM_LINES_ADJACENCY &&
- rast_prim != PIPE_PRIM_LINE_STRIP_ADJACENCY)
+ if (!util_prim_is_lines(rast_prim))
return false;
if (rast_prim == sctx->last_rast_prim &&
rs->pa_sc_line_stipple == sctx->last_sc_line_stipple)
return false;
/* For lines, reset the stipple pattern at each primitive. Otherwise,
* reset the stipple pattern at each packet (line strips, line loops).
*/
radeon_set_context_reg(cs, R_028A0C_PA_SC_LINE_STIPPLE,
@@ -1268,23 +1264,22 @@ void si_draw_vbo(struct pipe_context *ctx, const struct
pipe_draw_info *info)
rast_prim = sctx->gs_shader.cso->gs_output_prim;
else if (sctx->tes_shader.cso) {
if
(sctx->tes_shader.cso->info.properties[TGSI_PROPERTY_TES_POINT_MODE])
rast_prim = PIPE_PRIM_POINTS;
else
rast_prim =
sctx->tes_shader.cso->info.properties[TGSI_PROPERTY_TES_PRIM_MODE];
} else
rast_prim = info->mode;
if (rast_prim != sctx->current_rast_prim) {
- bool old_is_poly = sctx->current_rast_prim >=
PIPE_PRIM_TRIANGLES;
- bool new_is_poly = rast_prim >= PIPE_PRIM_TRIANGLES;
- if (old_is_poly != new_is_poly)
+ if (util_prim_is_points_or_lines(sctx->current_rast_prim) !=
+ util_prim_is_points_or_lines(rast_prim))
si_mark_atom_dirty(sctx, &sctx->atoms.s.guardband);
sctx->current_rast_prim = rast_prim;
sctx->do_update_shaders = true;
}
if (sctx->tes_shader.cso &&
sctx->screen->has_ls_vgpr_init_bug) {
/* Determine whether the LS VGPR fix should be applied.
*
diff --git a/src/gallium/drivers/radeonsi/si_state_shaders.c
b/src/gallium/drivers/radeonsi/si_state_shaders.c
index 7f9f9c4cd4a..aa270ebcb4d 100644
--- a/src/gallium/drivers/radeonsi/si_state_shaders.c
+++ b/src/gallium/drivers/radeonsi/si_state_shaders.c
@@ -1412,24 +1412,22 @@ static inline void si_shader_selector_key(struct
pipe_context *ctx,
}
/* Disable unwritten outputs (if WRITE_ALL_CBUFS isn't
enabled). */
if (!key->part.ps.epilog.last_cbuf) {
key->part.ps.epilog.spi_shader_col_format &=
sel->colors_written_4bit;
key->part.ps.epilog.color_is_int8 &=
sel->info.colors_written;
key->part.ps.epilog.color_is_int10 &=
sel->info.colors_written;
}
if (rs) {
- bool is_poly = (sctx->current_rast_prim >=
PIPE_PRIM_TRIANGLES &&
- sctx->current_rast_prim <=
PIPE_PRIM_POLYGON) ||
- sctx->current_rast_prim >=
PIPE_PRIM_TRIANGLES_ADJACENCY;
- bool is_line = !is_poly && sctx->current_rast_prim !=
PIPE_PRIM_POINTS;
+ bool is_poly =
!util_prim_is_points_or_lines(sctx->current_rast_prim);
+ bool is_line =
util_prim_is_lines(sctx->current_rast_prim);
key->part.ps.prolog.color_two_side = rs->two_side &&
sel->info.colors_read;
key->part.ps.prolog.flatshade_colors = rs->flatshade &&
sel->info.colors_read;
if (sctx->queued.named.blend) {
key->part.ps.epilog.alpha_to_one =
sctx->queued.named.blend->alpha_to_one &&
rs->multisample_enable;
}
key->part.ps.prolog.poly_stipple =
rs->poly_stipple_enable && is_poly;
diff --git a/src/gallium/drivers/radeonsi/si_state_viewport.c
b/src/gallium/drivers/radeonsi/si_state_viewport.c
index 97b1b89b48b..d16c3e7e41b 100644
--- a/src/gallium/drivers/radeonsi/si_state_viewport.c
+++ b/src/gallium/drivers/radeonsi/si_state_viewport.c
@@ -186,21 +186,21 @@ static void si_emit_guardband(struct si_context *ctx)
bottom = ( max_range - vp.translate[1]) / vp.scale[1];
assert(left <= -1 && top <= -1 && right >= 1 && bottom >= 1);
guardband_x = MIN2(-left, right);
guardband_y = MIN2(-top, bottom);
discard_x = 1.0;
discard_y = 1.0;
- if (unlikely(ctx->current_rast_prim < PIPE_PRIM_TRIANGLES) &&
+ if (unlikely(util_prim_is_points_or_lines(ctx->current_rast_prim)) &&
ctx->queued.named.rasterizer) {
/* When rendering wide points or lines, we need to be more
* conservative about when to discard them entirely. */
const struct si_state_rasterizer *rs =
ctx->queued.named.rasterizer;
float pixels;
if (ctx->current_rast_prim == PIPE_PRIM_POINTS)
pixels = rs->max_point_size;
else
pixels = rs->line_width;
--
2.17.0
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