Bump. On Fri, Jun 1, 2018 at 2:40 PM Anuj Phogat <anuj.pho...@gmail.com> wrote: > > CACHE_MODE_SS is not listed in gfxspecs table for user mode > non-privileged registers. So, making any changes from Mesa > will do nothing. Kernel is already setting this bit in > CACHE_MODE_SS register which is saved/restored to/from > the HW context image. > > Signed-off-by: Anuj Phogat <anuj.pho...@gmail.com> > Cc: Lionel Landwerlin <lionel.g.landwer...@intel.com> > --- > src/mesa/drivers/dri/i965/brw_state_upload.c | 4 ---- > 1 file changed, 4 deletions(-) > > diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c > b/src/mesa/drivers/dri/i965/brw_state_upload.c > index d8273aa5734..757426407c3 100644 > --- a/src/mesa/drivers/dri/i965/brw_state_upload.c > +++ b/src/mesa/drivers/dri/i965/brw_state_upload.c > @@ -64,10 +64,6 @@ brw_upload_initial_gpu_state(struct brw_context *brw) > brw_upload_invariant_state(brw); > > if (devinfo->gen == 10 || devinfo->gen == 11) { > - brw_load_register_imm32(brw, GEN10_CACHE_MODE_SS, > - > REG_MASK(GEN10_FLOAT_BLEND_OPTIMIZATION_ENABLE) | > - GEN10_FLOAT_BLEND_OPTIMIZATION_ENABLE); > - > /* From gen10 workaround table in h/w specs: > * > * "On 3DSTATE_3D_MODE, driver must always program bits 31:16 of DW1 > -- > 2.17.0 > _______________________________________________ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev